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fpga: x400: Add x410_400_128_rfnoc_image_core

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Original-commit: 13c03d4c2f366b41f5dd526326775a499a21514c
This commit is contained in:
Wade Fife
2022-03-14 21:34:23 -05:00
parent 29ab52420f
commit 37e0f51d67
5 changed files with 1613 additions and 3 deletions
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top/x400/Makefile
+22 -3
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@@ -53,6 +53,9 @@ X410_X1_200: DEFS += $(QSFP0_10GBE) RFBW_200M=1 DRAM_CH=4*$(D
X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4_200: DEFS += $(QSFP0_4X10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=0
X410_X1_400: DEFS += $(QSFP0_10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_X4_400: DEFS += $(QSFP0_4X10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_C1_400: DEFS += $(QSFP0_100GBE) RFBW_400M=1 DRAM_CH=0
X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0
@@ -63,9 +66,10 @@ DRAM ?= 1
DEFS += $(OPTIONS)
# Defaults specific to the various targets:
X410_100_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_100_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_100_static_router.hex)
X410_200_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
X410_400_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
X410_100_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_100_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_100_static_router.hex)
X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
X410_400_128_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_128_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_128_static_router.hex)
# Option to stop after RTL elaboration. Use this flag as a synthesis check.
@@ -110,6 +114,9 @@ vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID
##X410_X1_200 | 200 MHz | 10 GbE (Lane 0) | None | 64b x 4 Ch
##X410_XG_200 | 200 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
##X410_X4_200 | 200 MHz | 4 x 10 GbE | None | 64b x 4 Ch
##X410_X1_400 | 400 MHz | 10 GbE (Lane 0) | None | 128b x 4 Ch
##X410_XG_400 | 400 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch
##X410_X4_400 | 400 MHz | 4 x 10 GbE | None | 128b x 4 Ch
##X410_C1_400 | 400 MHz | 100 GbE | None | None
##X410_CG_400 | 400 MHz | 100 GbE | 100 GbE | None
##* Note: Not all targets are shipped with UHD
@@ -138,6 +145,18 @@ X410_X4_200: build/usrp_x410_fpga_X4_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X4_200)
X410_X1_400: build/usrp_x410_fpga_X1_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
$(call post_build,X410,X1_400)
X410_XG_400: build/usrp_x410_fpga_XG_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
$(call post_build,X410,XG_400)
X410_X4_400: build/usrp_x410_fpga_X4_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
$(call post_build,X410,X4_400)
X410_C1_400: build/usrp_x410_fpga_C1_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,C1_400)