fpga: rfnoc: Move synthesizable code from sim to lib

Original-commit: d9f8c08dfb1afe98c35c5911125c6eead869713f

lib/rfnoc/blocks/rfnoc_block_addsub/rfnoc_block_addsub_tb.sv

@@ -23,7 +23,8 @@ module rfnoc_block_addsub_tb #(
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv

@@ -25,7 +25,8 @@ module rfnoc_block_axi_ram_fifo_tb #(
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
 
   `include "axi_ram_fifo_regs.vh"

lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv

@@ -15,7 +15,8 @@ module rfnoc_block_ddc_tb();
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
   import PkgMath::*;

lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv

@@ -15,7 +15,8 @@ module rfnoc_block_duc_tb();
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
 
   `include "rfnoc_block_duc_regs.vh"

lib/rfnoc/blocks/rfnoc_block_fft/fft_packetize_tb/fft_packetize_tb.sv

@@ -39,15 +39,13 @@ module fft_packetize_tb #(
   `include "test_exec.svh"
   import PkgTestExec::*;
 
+  import rfnoc_chdr_utils_pkg::*;
   import PkgAxiStreamBfm::*;
   import PkgRandom::*;
   import PkgChdrData::*;
 
   `include "usrp_utils.svh"
 
-  `include "rfnoc_chdr_utils.vh"
-  import PkgChdrUtils::*;
-
   import fft_packetize_pkg::*;
 
   localparam real CLK_PERIOD = 10.0;

lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft_tb.sv

@@ -35,7 +35,8 @@ module rfnoc_block_fft_tb #(
   `include "usrp_utils.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter_tb.sv

@@ -17,7 +17,8 @@ module rfnoc_block_fir_filter_tb #(
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
 
   `include "rfnoc_fir_filter_regs.vh"

lib/rfnoc/blocks/rfnoc_block_fosphor/rfnoc_block_fosphor_tb.sv

@@ -16,7 +16,8 @@ module rfnoc_block_fosphor_tb;
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_keep_one_in_n/rfnoc_block_keep_one_in_n_tb.sv

@@ -15,7 +15,8 @@ module rfnoc_block_keep_one_in_n_tb;
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_license_check/rfnoc_block_license_check_tb.sv

@@ -16,7 +16,7 @@ module rfnoc_block_license_check_tb;
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv

@@ -18,7 +18,8 @@ module rfnoc_block_logpwr_tb #(
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv

@@ -16,7 +16,8 @@ module rfnoc_block_moving_avg_tb;
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink_tb.sv

@@ -21,7 +21,8 @@ module rfnoc_block_null_src_sink_tb #(
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_tb.sv

@@ -23,7 +23,8 @@ module rfnoc_block_radio_tb #(
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgAxisCtrlBfm::*;
   import PkgChdrBfm::*;

lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay_tb.sv

@@ -40,7 +40,8 @@ module rfnoc_block_replay_tb#(
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv

@@ -19,7 +19,8 @@ module rfnoc_block_siggen_tb #(
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv

@@ -23,7 +23,8 @@ module rfnoc_block_split_stream_tb #(
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv

@@ -20,7 +20,8 @@ module rfnoc_block_switchboard_tb #(
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_vector_iir/rfnoc_block_vector_iir_tb.sv

@@ -16,7 +16,8 @@ module rfnoc_block_vector_iir_tb;
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv

@@ -16,7 +16,8 @@ module rfnoc_block_window_tb;
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 

lib/rfnoc/core/rfnoc_chdr_utils_pkg.sv

@@ -7,11 +7,241 @@
 //
 // Description:
 //
-//   Package containing constants and functions for working with CHDR.
+//   Package containing constants, functions, and types for working with RFNoC
+//   CHDR.
 //
 
 package rfnoc_chdr_utils_pkg;
 
+  // Import Verilog functions to avoid duplication here
   `include "rfnoc_chdr_utils.vh"
 
+
+  //---------------------------------------------------------------------------
+  // AXIS-CHDR Definitions
+  //---------------------------------------------------------------------------
+
+  // CHDR header fields
+  typedef enum bit [2:0] {
+    CHDR_MANAGEMENT   = 3'd0,
+    CHDR_STRM_STATUS  = 3'd1,
+    CHDR_STRM_CMD     = 3'd2,
+    CHDR_RESERVED_0   = 3'd3,
+    CHDR_CONTROL      = 3'd4,
+    CHDR_RESERVED_1   = 3'd5,
+    CHDR_DATA_NO_TS   = 3'd6,
+    CHDR_DATA_WITH_TS = 3'd7
+  } chdr_pkt_type_t;                    // CHDR Packet Type
+
+  typedef bit [ 5:0] chdr_vc_t;         // CHDR Virtual Channel field
+  typedef bit [ 0:0] chdr_eob_t;        // CHDR End of Burst field
+  typedef bit [ 0:0] chdr_eov_t;        // CHDR End of Vector field
+  typedef bit [ 4:0] chdr_num_mdata_t;  // CHDR Num Metadata field
+  typedef bit [15:0] chdr_seq_num_t;    // CHDR SeqNum field
+  typedef bit [15:0] chdr_length_t;     // CHDR Length field
+  typedef bit [15:0] chdr_epid_t;       // CHDR EPID field
+  typedef bit [63:0] chdr_timestamp_t;  // CHDR Timestamp field
+
+  // CHDR Context Field Identifiers
+  typedef enum bit [3:0] {
+    CTXT_FIELD_HDR    = 4'd0,
+    CTXT_FIELD_HDR_TS = 4'd1,
+    CTXT_FIELD_TS     = 4'd2,
+    CTXT_FIELD_MDATA  = 4'd3
+  } chdr_context_type_t;
+
+
+  //---------------------------------------------------------------------------
+  // AXIS-Ctrl Definitions
+  //---------------------------------------------------------------------------
+
+  // The fundamental unit of the AXIS-Ctrl (control) bus, which is always 32 bits
+  typedef logic [31:0] ctrl_word_t;
+
+  typedef enum bit [3:0] {
+    CTRL_OP_SLEEP      = 4'd0,
+    CTRL_OP_WRITE      = 4'd1,
+    CTRL_OP_READ       = 4'd2,
+    CTRL_OP_WRITE_READ = 4'd3,
+    CTRL_OP_RESERVED_0 = 4'd4,
+    CTRL_OP_RESERVED_1 = 4'd5,
+    CTRL_OP_RESERVED_2 = 4'd6,
+    CTRL_OP_RESERVED_3 = 4'd7,
+    CTRL_OP_RESERVED_4 = 4'd8,
+    CTRL_OP_RESERVED_5 = 4'd9
+  } ctrl_opcode_t;                    // Control OpCode Type
+
+  typedef enum bit [1:0] {
+    CTRL_STS_OKAY    = 2'd0,
+    CTRL_STS_CMDERR  = 2'd1,
+    CTRL_STS_TSERR   = 2'd2,
+    CTRL_STS_WARNING = 2'd3
+  } ctrl_status_t;                    // Control OpCode Type
+
+  typedef bit [ 5:0] ctrl_seq_num_t;  // AXIS-Ctrl SeqNum field
+  typedef bit [ 3:0] ctrl_num_data_t; // AXIS-Ctrl NumData field
+  typedef bit [ 9:0] ctrl_port_t;     // AXIS-Ctrl source/destination port field
+  typedef bit [ 3:0] ctrl_byte_en_t;  // AXIS-Ctrl ByteEnable field
+  typedef bit [19:0] ctrl_address_t;  // AXIS-Ctrl Address field
+
+
+  //---------------------------------------------------------------------------
+  // CHDR Type-Specific Definitions
+  //---------------------------------------------------------------------------
+
+  // CHDR stream status packet status field
+  typedef enum bit [3:0] {
+    STRS_OKAY    = 4'd0,
+    STRS_CMDERR  = 4'd1,
+    STRS_SEQERR  = 4'd2,
+    STRS_DATAERR = 4'd3,
+    STRS_RTERR   = 4'd4
+  } chdr_strs_status_t;
+
+  // CHDR stream command packet opcode field
+  typedef enum bit [3:0] {
+    STRC_INIT    = 4'd0,
+    STRC_PING    = 4'd1,
+    STRC_RESYNC  = 4'd2
+  } chdr_strc_opcode_t;
+
+  // CHDR management packet CHDR width field
+  typedef enum bit [2:0] {
+    CHDR_W_64      = 3'd0,
+    CHDR_W_128     = 3'd1,
+    CHDR_W_256     = 3'd2,
+    CHDR_W_512     = 3'd3,
+    CHDR_W_INVALID = 3'd7
+  } chdr_mgmt_width_t;
+
+  // CHDR management packet OpCode field
+  typedef enum bit [7:0] {
+    MGMT_OP_NOP         = 8'd0,
+    MGMT_OP_ADVERTISE   = 8'd1,
+    MGMT_OP_SEL_DEST    = 8'd2,
+    MGMT_OP_RETURN      = 8'd3,
+    MGMT_OP_INFO_REQ    = 8'd4,
+    MGMT_OP_INFO_RESP   = 8'd5,
+    MGMT_OP_CFG_WR_REQ  = 8'd6,
+    MGMT_OP_CFG_RD_REQ  = 8'd7,
+    MGMT_OP_CFG_RD_RESP = 8'd8
+  } chdr_mgmt_opcode_t;
+
+  function automatic chdr_mgmt_width_t translate_chdr_w(int width_in_bits);
+    case (width_in_bits)
+      64:      return CHDR_W_64;
+      128:     return CHDR_W_128;
+      256:     return CHDR_W_256;
+      512:     return CHDR_W_512;
+      default: return CHDR_W_INVALID;
+    endcase
+  endfunction : translate_chdr_w
+
+  function automatic int translate_bit_w(chdr_mgmt_width_t chdr_width);
+    case (chdr_width)
+      CHDR_W_64:  return 64;
+      CHDR_W_128: return 128;
+      CHDR_W_256: return 256;
+      CHDR_W_512: return 512;
+      default:    return -1;
+    endcase
+  endfunction : translate_bit_w
+
+
+  //---------------------------------------------------------------------------
+  // Packet Data Structures
+  //---------------------------------------------------------------------------
+
+  // CHDR packet header
+  typedef struct packed {
+    chdr_vc_t        vc;
+    chdr_eob_t       eob;
+    chdr_eov_t       eov;
+    chdr_pkt_type_t  pkt_type;
+    chdr_num_mdata_t num_mdata;
+    chdr_seq_num_t   seq_num;
+    chdr_length_t    length;
+    chdr_epid_t      dst_epid;
+  } chdr_header_t;
+
+  // AXIS-Ctrl packet header
+  typedef struct packed {
+    // Word 1
+    bit [ 5:0]      _rsvd_0;
+    ctrl_port_t     rem_dst_port;
+    chdr_epid_t     rem_dst_epid;
+    // Word 0
+    bit             is_ack;
+    bit             has_time;
+    ctrl_seq_num_t  seq_num;
+    ctrl_num_data_t num_data;
+    ctrl_port_t     src_port;
+    ctrl_port_t     dst_port;
+  } axis_ctrl_header_t;
+
+  // AXIS-Ctrl packet header
+  typedef struct packed {
+    ctrl_status_t status;
+    bit [ 1:0]    _rsvd_0;
+    ctrl_opcode_t op_code;
+    bit [ 3:0]    byte_enable;
+    bit [19:0]    address;
+  } ctrl_op_word_t;
+
+  // Ctrl packet header when in the payload of a CHDR packet
+  typedef struct packed {
+    bit [15:0]      _rsvd_0;
+    chdr_epid_t     src_epid;
+    bit             is_ack;
+    bit             has_time;
+    ctrl_seq_num_t  seq_num;
+    ctrl_num_data_t num_data;
+    ctrl_port_t     src_port;
+    ctrl_port_t     dst_port;
+  } chdr_ctrl_header_t;
+
+  // CHDR stream status packet payload
+  typedef struct packed {
+    // Word 3
+    bit [47:0]         status_info;
+    bit [15:0]         buff_info;
+    // Word 2
+    bit [63:0]         xfer_count_bytes;
+    // Word 1
+    bit [39:0]         xfer_count_pkts;
+    bit [23:0]         capacity_pkts;
+    // Word 0
+    bit [39:0]         capacity_bytes;
+    bit [ 3:0]         _rsvd_0;
+    chdr_strs_status_t status;
+    chdr_epid_t        src_epid;
+  } chdr_str_status_t;
+
+  // CHDR stream command packet payload
+  typedef struct packed {
+    // Word 1
+    bit [63:0]         num_bytes;
+    // Word 0
+    bit [39:0]         num_pkts;
+    bit [ 3:0]         op_data;
+    chdr_strc_opcode_t op_code;
+    chdr_epid_t        src_epid;
+  } chdr_str_command_t;
+
+  // CHDR management packet header
+  typedef struct packed {
+    bit [15:0]        prot_ver;
+    chdr_mgmt_width_t chdr_width;
+    bit [18:0]        _rsvd_0;
+    bit [ 9:0]        num_hops;
+    chdr_epid_t       src_epid;
+  } chdr_mgmt_header_t;
+
+  // CHDR management packet operation
+  typedef struct packed {
+    bit [47:0]         op_payload;
+    chdr_mgmt_opcode_t op_code;
+    bit [ 7:0]         ops_pending;
+  } chdr_mgmt_op_t;
+
 endpackage : rfnoc_chdr_utils_pkg

lib/rfnoc/crossbar/chdr_crossbar_nxn_tb/chdr_crossbar_nxn_tb.sv

@@ -61,7 +61,8 @@ module chdr_crossbar_nxn_tb #(
 
   import PkgTestExec::*;
   import PkgChdrBfm::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
 
 
   //---------------------------------------------------------------------------

lib/rfnoc/sim/axis_pyld_ctxt_converter_tb/axis_pyld_ctxt_converter_tb.sv

@@ -20,7 +20,7 @@ module axis_pyld_ctxt_converter_tb;
 
   import PkgTestExec::*;
   import PkgAxiStreamBfm::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
   import PkgChdrBfm::*;
 
   // Parameters

lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv

@@ -29,7 +29,8 @@ module chdr_resize_tb #(
   `define DIV_CEIL(N, D) (((N)+(D)-1)/(D))    // ceiling(N/D)
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgChdrBfm::*;
   import PkgRandom::*;
 

lib/rfnoc/sim/chdr_stream_endpoint_tb/chdr_stream_endpoint_tb.sv

@@ -22,7 +22,8 @@ module chdr_stream_endpoint_tb#(
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgChdrBfm::*;
 
   // Clocks and resets

lib/rfnoc/sim/ctrlport_endpoint_tb/ctrlport_endpoint_tb.sv

@@ -15,7 +15,7 @@ module ctrlport_endpoint_tb;
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
   import PkgAxisCtrlBfm::*;
 
   // Parameters

lib/rfnoc/sim/eth_ipv4_interface_tb/eth_ipv4_interface_tb.sv

@@ -43,7 +43,8 @@ module eth_ipv4_interface_tb #(
   `include "../../xport_sv/eth_regs.vh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgChdrIfaceBfm::*;
   import PkgAxiStreamBfm::*;
   import PkgChdrBfm::*;

lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/rfnoc_ta_x4xx_eth_tb/rfnoc_ta_x4xx_eth_tb.sv

@@ -37,7 +37,8 @@ module rfnoc_ta_x4xx_eth_tb #(
   import PkgAxiStreamBfm::*;
   import PkgAxiLiteBfm::*;
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgChdrBfm::*;
   import PkgEthernet::*;
 

lib/rfnoc/xport_sv/eth_interface_tb/eth_ifc_tb.sv

@@ -41,7 +41,8 @@ module eth_ifc_tb #(
   `include "test_exec.svh"
   import PkgAxiStreamBfm::*;
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgChdrBfm::*;
   import PkgEthernet::*;
 

sim/rfnoc/Makefile.srcs

@@ -27,7 +27,7 @@ PkgAxiStreamBfm.sv \
 PkgAxiLiteBfm.sv \
 PkgEthernet.sv \
 PkgChdrData.sv \
-PkgChdrUtils.sv \
+../../lib/rfnoc/core/rfnoc_chdr_utils_pkg.sv \
 PkgChdrBfm.sv \
 PkgAxisCtrlBfm.sv \
 PkgRfnocItemUtils.sv \

sim/rfnoc/PkgAxisCtrlBfm.sv

@@ -13,7 +13,7 @@
 
 package PkgAxisCtrlBfm;
 
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
   import PkgAxiStreamBfm::*;
   export PkgAxiStreamBfm::*;
 

sim/rfnoc/PkgChdrBfm.sv

@@ -12,10 +12,21 @@
 
 package PkgChdrBfm;
 
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgAxiStreamBfm::*;
 
 
+  //---------------------------------------------------------------------------
+  // CHDR Management Packet
+  //---------------------------------------------------------------------------
+
+  typedef struct {
+    chdr_mgmt_header_t  header;
+    chdr_mgmt_op_t      ops[$];
+  } chdr_mgmt_t;
+
+
   //---------------------------------------------------------------------------
   // CHDR Packet Class
   //---------------------------------------------------------------------------

sim/rfnoc/PkgChdrIfaceBfm.sv

@@ -11,7 +11,8 @@
 
 package PkgChdrIfaceBfm;
 
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgChdrBfm::*;
 
 

sim/rfnoc/PkgChdrUtils.sv

@@ -1,248 +0,0 @@
-//
-// Copyright 2019 Ettus Research, A National Instruments Company
-//
-// SPDX-License-Identifier: LGPL-3.0-or-later
-//
-// Module: PkgChdrUtils
-//
-// Description: Various types, constants, and functions for interacting with 
-// the RFNoC CHDR bus infrastructure.
-//
-
-
-
-package PkgChdrUtils;
-
-  import PkgChdrData::*;
-
-
-  //---------------------------------------------------------------------------
-  // Type Definitions
-  //---------------------------------------------------------------------------
-
-  //----------------------
-  // AXIS-CHDR Definitions
-  //----------------------
-
-  // Expose the CHDR word and item/sample data types and methods in the
-  // ChdrData class. The width of these types is a class parameter. 
-  export PkgChdrData::ChdrData;
-
-  // CHDR header fields
-  typedef enum bit [2:0] { 
-    CHDR_MANAGEMENT   = 3'd0,
-    CHDR_STRM_STATUS  = 3'd1,
-    CHDR_STRM_CMD     = 3'd2,
-    CHDR_RESERVED_0   = 3'd3,
-    CHDR_CONTROL      = 3'd4,
-    CHDR_RESERVED_1   = 3'd5,
-    CHDR_DATA_NO_TS   = 3'd6,
-    CHDR_DATA_WITH_TS = 3'd7
-  } chdr_pkt_type_t;                    // CHDR Packet Type
-
-  typedef bit [ 5:0] chdr_vc_t;         // CHDR Virtual Channel field
-  typedef bit [ 0:0] chdr_eob_t;        // CHDR End of Burst field
-  typedef bit [ 0:0] chdr_eov_t;        // CHDR End of Vector field
-  typedef bit [ 4:0] chdr_num_mdata_t;  // CHDR Num Metadata field
-  typedef bit [15:0] chdr_seq_num_t;    // CHDR SeqNum field
-  typedef bit [15:0] chdr_length_t;     // CHDR Length field
-  typedef bit [15:0] chdr_epid_t;       // CHDR EPID field
-  typedef bit [63:0] chdr_timestamp_t;  // CHDR Timestamp field
-
-  // CHDR Context Field Identifiers
-  typedef enum bit [3:0] { 
-    CONTEXT_FIELD_HDR    = 4'd0,
-    CONTEXT_FIELD_HDR_TS = 4'd1,
-    CONTEXT_FIELD_TS     = 4'd2,
-    CONTEXT_FIELD_MDATA  = 4'd3
-  } chdr_context_type_t;
-
-  //----------------------
-  // AXIS-Ctrl Definitions
-  //----------------------
-
-  // The fundamental unit of the AXIS-Ctrl (control) bus, which is always 32 bits
-  typedef logic [31:0] ctrl_word_t;
-
-  typedef enum bit [3:0] { 
-    CTRL_OP_SLEEP      = 4'd0,
-    CTRL_OP_WRITE      = 4'd1,
-    CTRL_OP_READ       = 4'd2,
-    CTRL_OP_WRITE_READ = 4'd3,
-    CTRL_OP_RESERVED_0 = 4'd4,
-    CTRL_OP_RESERVED_1 = 4'd5,
-    CTRL_OP_RESERVED_2 = 4'd6,
-    CTRL_OP_RESERVED_3 = 4'd7,
-    CTRL_OP_RESERVED_4 = 4'd8,
-    CTRL_OP_RESERVED_5 = 4'd9
-  } ctrl_opcode_t;                    // Control OpCode Type
-
-  typedef enum bit [1:0] { 
-    CTRL_STS_OKAY    = 2'd0,
-    CTRL_STS_CMDERR  = 2'd1,
-    CTRL_STS_TSERR   = 2'd2,
-    CTRL_STS_WARNING = 2'd3
-  } ctrl_status_t;                    // Control OpCode Type
-
-  typedef bit  [5:0] ctrl_seq_num_t;  // AXIS-Ctrl SeqNum field
-  typedef bit  [3:0] ctrl_num_data_t; // AXIS-Ctrl NumData field
-  typedef bit  [9:0] ctrl_port_t;     // AXIS-Ctrl source/destination port field
-  typedef bit  [3:0] ctrl_byte_en_t;  // AXIS-Ctrl ByteEnable field
-  typedef bit [19:0] ctrl_address_t;  // AXIS-Ctrl Address field
-
-  //-------------------------------
-  // CHDR Type-Specific Definitions
-  //-------------------------------
-
-  // CHDR Status packet fields
-  typedef enum bit [3:0] {
-    STRS_OKAY    = 4'd0,
-    STRS_CMDERR  = 4'd1,
-    STRS_SEQERR  = 4'd2,
-    STRS_DATAERR = 4'd3,
-    STRS_RTERR   = 4'd4
-  } chdr_strs_status_t;  // CHDR stream status packet status field
-
-  // CHDR Control packet fields
-  typedef enum bit [3:0] {
-    STRC_INIT    = 4'd0,
-    STRC_PING    = 4'd1,
-    STRC_RESYNC  = 4'd2
-  } chdr_strc_opcode_t;  // CHDR stream command packet opcode filed
-
-  // CHDR Management packet field
-  typedef enum bit [2:0] {
-    CHDR_W_64      = 3'd0,
-    CHDR_W_128     = 3'd1,
-    CHDR_W_256     = 3'd2,
-    CHDR_W_512     = 3'd3,
-    CHDR_W_INVALID = 3'd7
-  } chdr_mgmt_width_t;   // CHDR management packet CHDR Width field
-
-  function automatic chdr_mgmt_width_t translate_chdr_w(int bitwidth);
-    case (bitwidth)
-      64:      return CHDR_W_64;
-      128:     return CHDR_W_128;
-      256:     return CHDR_W_256;
-      512:     return CHDR_W_512;
-      default: return CHDR_W_INVALID;
-    endcase
-  endfunction : translate_chdr_w
-
-  typedef enum bit [7:0] {
-    MGMT_OP_NOP         = 8'd0,
-    MGMT_OP_ADVERTISE   = 8'd1,
-    MGMT_OP_SEL_DEST    = 8'd2,
-    MGMT_OP_RETURN      = 8'd3,
-    MGMT_OP_INFO_REQ    = 8'd4,
-    MGMT_OP_INFO_RESP   = 8'd5,
-    MGMT_OP_CFG_WR_REQ  = 8'd6,
-    MGMT_OP_CFG_RD_REQ  = 8'd7,
-    MGMT_OP_CFG_RD_RESP = 8'd8
-  } chdr_mgmt_opcode_t;  // CHDR management packet OpCode field
-
-
-  //---------------------------------------------------------------------------
-  // Packet Data Structures
-  //---------------------------------------------------------------------------
-
-  // CHDR packet header
-  typedef struct packed {
-    chdr_vc_t        vc;
-    chdr_eob_t       eob;
-    chdr_eov_t       eov;
-    chdr_pkt_type_t  pkt_type;
-    chdr_num_mdata_t num_mdata;
-    chdr_seq_num_t   seq_num;
-    chdr_length_t    length;
-    chdr_epid_t      dst_epid;
-  } chdr_header_t;
-
-  // AXIS-Ctrl packet header
-  typedef struct packed {
-    // Word 1
-    bit [ 5:0]      _rsvd_0;
-    ctrl_port_t     rem_dst_port;
-    chdr_epid_t     rem_dst_epid;
-    // Word 0
-    bit             is_ack;
-    bit             has_time;
-    ctrl_seq_num_t  seq_num;
-    ctrl_num_data_t num_data;
-    ctrl_port_t     src_port;
-    ctrl_port_t     dst_port;
-  } axis_ctrl_header_t;
-
-  // AXIS-Ctrl packet header
-  typedef struct packed {
-    ctrl_status_t status;
-    bit [ 1:0]    _rsvd_0;
-    ctrl_opcode_t op_code;
-    bit [ 3:0]    byte_enable;
-    bit [19:0]    address;
-  } ctrl_op_word_t;
-
-  // Ctrl packet header when in the payload of a CHDR packet
-  typedef struct packed {
-    bit [15:0]      _rsvd_0;
-    chdr_epid_t     src_epid;
-    bit             is_ack;
-    bit             has_time;
-    ctrl_seq_num_t  seq_num;
-    ctrl_num_data_t num_data;
-    ctrl_port_t     src_port;
-    ctrl_port_t     dst_port;
-  } chdr_ctrl_header_t;
-
-  // CHDR stream status packet payload
-  typedef struct packed {
-    // Word 3
-    bit [47:0]          status_info;
-    bit [15:0]          buff_info;
-    // Word 2
-    bit [63:0]          xfer_count_bytes;
-    // Word 1
-    bit [39:0]          xfer_count_pkts;
-    bit [23:0]          capacity_pkts;
-    // Word 0
-    bit [39:0]          capacity_bytes;
-    bit [ 3:0]          _rsvd_0;
-    chdr_strs_status_t  status;
-    chdr_epid_t         src_epid;
-  } chdr_str_status_t;
-
-  // CHDR stream command packet payload
-  typedef struct packed {
-    // Word 1
-    bit [63:0]          num_bytes;
-    // Word 0
-    bit [39:0]          num_pkts;
-    bit [ 3:0]          op_data;
-    chdr_strc_opcode_t  op_code;
-    chdr_epid_t         src_epid;
-  } chdr_str_command_t;
-
-  // CHDR management packet header
-  typedef struct packed {
-    bit [15:0]          prot_ver;
-    chdr_mgmt_width_t   chdr_width;
-    bit [18:0]          _rsvd_0;
-    bit [ 9:0]          num_hops;
-    chdr_epid_t         src_epid;
-  } chdr_mgmt_header_t;
-
-  // CHDR management packet operation
-  typedef struct packed {
-    bit [47:0]          op_payload;
-    chdr_mgmt_opcode_t  op_code;
-    bit [ 7:0]          ops_pending;
-  } chdr_mgmt_op_t;
-
-  // CHDR management packet
-  typedef struct {
-    chdr_mgmt_header_t  header;
-    chdr_mgmt_op_t      ops[$];
-  } chdr_mgmt_t;
-
-
-endpackage : PkgChdrUtils

sim/rfnoc/PkgCtrlIfaceBfm.sv

@@ -12,7 +12,7 @@
 
 package PkgCtrlIfaceBfm;
 
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
   import PkgAxisCtrlBfm::*;
 
 

sim/rfnoc/PkgRfnocBlockCtrlBfm.sv

@@ -77,7 +77,8 @@ endinterface : RfnocBackendIf
 
 package PkgRfnocBlockCtrlBfm;
 
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgChdrBfm::*;
   import PkgCtrlIfaceBfm::*;
   import PkgChdrIfaceBfm::*;

sim/rfnoc/PkgRfnocItemUtils.sv

@@ -17,7 +17,7 @@
 
 package PkgRfnocItemUtils;
 
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
 
   //---------------------------------------------------------------------------
   // Item Data Buffer
@@ -31,7 +31,7 @@ package PkgRfnocItemUtils;
 
     localparam ITEM_W = $bits(item_t);
 
-    // Redefine these types from PkgChdrUtils to workaround Vivado 2019.1 bug
+    // Redefine these types from rfnoc_chdr_utils_pkg to workaround Vivado 2019.1 bug
     typedef logic [CHDR_W-1:0] chdr_word_t;
     typedef chdr_word_t        chdr_word_queue_t[$];
 

sim/rfnoc/test/ChdrIfaceBfm/ChdrIfaceBfm_tb.sv

@@ -18,7 +18,8 @@ module ChdrIfaceBfm_tb #(
   `include "test_exec.svh"
 
   import PkgTestExec::*;
-  import PkgChdrUtils::*;
+  import rfnoc_chdr_utils_pkg::*;
+  import PkgChdrData::*;
   import PkgChdrIfaceBfm::*;