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fpga: rfnoc: Move synthesizable code from sim to lib

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Original-commit: d9f8c08dfb1afe98c35c5911125c6eead869713f
This commit is contained in:
Wade Fife
2025-03-17 17:47:16 -05:00
parent b4943f4a61
commit 37b8b0d017
38 changed files with 307 additions and 289 deletions
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lib/rfnoc/sim/axis_pyld_ctxt_converter_tb/axis_pyld_ctxt_converter_tb.sv
+1 -1
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@@ -20,7 +20,7 @@ module axis_pyld_ctxt_converter_tb;
import PkgTestExec::*;
import PkgAxiStreamBfm::*;
import PkgChdrUtils::*;
import rfnoc_chdr_utils_pkg::*;
import PkgChdrBfm::*;
// Parameters
lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv
+2 -1
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@@ -29,7 +29,8 @@ module chdr_resize_tb #(
`define DIV_CEIL(N, D) (((N)+(D)-1)/(D)) // ceiling(N/D)
import PkgTestExec::*;
import PkgChdrUtils::*;
import rfnoc_chdr_utils_pkg::*;
import PkgChdrData::*;
import PkgChdrBfm::*;
import PkgRandom::*;
lib/rfnoc/sim/chdr_stream_endpoint_tb/chdr_stream_endpoint_tb.sv
+2 -1
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@@ -22,7 +22,8 @@ module chdr_stream_endpoint_tb#(
`include "test_exec.svh"
import PkgTestExec::*;
import PkgChdrUtils::*;
import rfnoc_chdr_utils_pkg::*;
import PkgChdrData::*;
import PkgChdrBfm::*;
// Clocks and resets
lib/rfnoc/sim/ctrlport_endpoint_tb/ctrlport_endpoint_tb.sv
+1 -1
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@@ -15,7 +15,7 @@ module ctrlport_endpoint_tb;
`include "test_exec.svh"
import PkgTestExec::*;
import PkgChdrUtils::*;
import rfnoc_chdr_utils_pkg::*;
import PkgAxisCtrlBfm::*;
// Parameters
lib/rfnoc/sim/eth_ipv4_interface_tb/eth_ipv4_interface_tb.sv
+2 -1
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@@ -43,7 +43,8 @@ module eth_ipv4_interface_tb #(
`include "../../xport_sv/eth_regs.vh"
import PkgTestExec::*;
import PkgChdrUtils::*;
import rfnoc_chdr_utils_pkg::*;
import PkgChdrData::*;
import PkgChdrIfaceBfm::*;
import PkgAxiStreamBfm::*;
import PkgChdrBfm::*;