fpga: e31x: Cleanup MTU parameters

Original-commit: 55a1ef7e50d271459f44b98d55860bfb2bbe2d19

top/e31x/e31x.v

@@ -152,6 +152,9 @@ module e31x (
     CHDR_W_must_be_64_for_this_USRP();
   end
 
+  // Log base 2 of the maximum transmission unit (MTU) in bytes
+  localparam BYTE_MTU = $clog2(8192);
+
   // Constants
   localparam REG_AWIDTH = 14; // log2(0x4000)
   localparam REG_DWIDTH = 32;
@@ -421,6 +424,7 @@ module e31x (
     .DWIDTH(REG_DWIDTH),
     .AWIDTH(REG_AWIDTH),
     .PORTNUM(8'd1),
+    .BYTE_MTU(BYTE_MTU),
     .RFNOC_PROTOVER(RFNOC_PROTOVER),
     .NODE_INST(0)
   ) eth_internal_i (
@@ -866,6 +870,7 @@ module e31x (
     .FP_GPIO_WIDTH(FP_GPIO_WIDTH),
     .DB_GPIO_WIDTH(DB_GPIO_WIDTH),
     .CHDR_W(CHDR_W),
+    .BYTE_MTU(BYTE_MTU),
     .RFNOC_PROTOVER(RFNOC_PROTOVER)
   ) e31x_core_inst (
 

top/e31x/e31x_core.v

@@ -27,6 +27,7 @@ module e31x_core #(
   parameter FP_GPIO_WIDTH = 8,  // Front panel GPIO width
   parameter DB_GPIO_WIDTH = 16,  // Daughterboard GPIO width
   parameter CHDR_W = 64,
+  parameter BYTE_MTU = $clog2(8192),
   parameter RFNOC_PROTOVER  = {8'd1, 8'd0}
 )(
   // Clocks and resets
@@ -813,6 +814,7 @@ module e31x_core #(
 
   rfnoc_image_core #(
     .CHDR_W   (CHDR_W),
+    .MTU      (BYTE_MTU - $clog2(CHDR_W/8)),
     .PROTOVER (RFNOC_PROTOVER)
   ) rfnoc_image_core_i (
     .chdr_aclk               (bus_clk    ),