From 2a89218e950ce16d199d5246ea5e9576f83c7c29 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Max=20K=C3=B6hler?= Date: Fri, 8 Nov 2024 00:32:10 +0100 Subject: [PATCH] fpga: x400: add rf core ctrlport Original-commit: a9add0a6a5baefe7dcc8fbb5a39f01dc935c7a3e --- .../regmap/radio_ctrlport_regmap_utils.vh | 7 +++- top/x400/x4xx.sv | 33 +++++++++++++++++++ top/x400/x4xx_core.v | 15 +++++++++ top/x400/x4xx_core_common.v | 26 +++++++++++++-- 4 files changed, 78 insertions(+), 3 deletions(-) diff --git a/top/x400/regmap/radio_ctrlport_regmap_utils.vh b/top/x400/regmap/radio_ctrlport_regmap_utils.vh index 861752b..4633d97 100644 --- a/top/x400/regmap/radio_ctrlport_regmap_utils.vh +++ b/top/x400/regmap/radio_ctrlport_regmap_utils.vh @@ -13,6 +13,7 @@ // DB_WINDOW : 0x0 (x4xx_core_common.v) // RFDC_TIMING_WINDOW : 0x8000 (x4xx_core_common.v) + // RF_CORE_WINDOW : 0xA000 (x4xx_core_common.v) // DIO_WINDOW : 0xC000 (x4xx_core_common.v) //=============================================================================== @@ -29,7 +30,11 @@ // RFDC_TIMING_WINDOW Window (from x4xx_core_common.v) localparam RFDC_TIMING_WINDOW = 'h8000; // Window Offset - localparam RFDC_TIMING_WINDOW_SIZE = 'h4000; // size in bytes + localparam RFDC_TIMING_WINDOW_SIZE = 'h2000; // size in bytes + + // RF_CORE_WINDOW Window (from x4xx_core_common.v) + localparam RF_CORE_WINDOW = 'hA000; // Window Offset + localparam RF_CORE_WINDOW_SIZE = 'h2000; // size in bytes // DIO_WINDOW Window (from x4xx_core_common.v) localparam DIO_WINDOW = 'hC000; // Window Offset diff --git a/top/x400/x4xx.sv b/top/x400/x4xx.sv index c73b9e9..80b6e42 100644 --- a/top/x400/x4xx.sv +++ b/top/x400/x4xx.sv @@ -272,6 +272,7 @@ module x4xx ( `include "regmap/global_regs_regmap_utils.vh" `include "regmap/versioning_utils.vh" + `include "../../lib/rfnoc/core/ctrlport.vh" //--------------------------------------------------------------------------- @@ -1922,6 +1923,15 @@ module x4xx ( wire [31:0] db_ctrlport_resp_data [0:NUM_DBOARDS-1]; wire [ 1:0] db_ctrlport_resp_status [0:NUM_DBOARDS-1]; + // RF core ctrlport interface + wire rf_core_ctrlport_req_rd [0:NUM_DBOARDS-1]; + wire rf_core_ctrlport_req_wr [0:NUM_DBOARDS-1]; + wire [19:0] rf_core_ctrlport_req_addr [0:NUM_DBOARDS-1]; + wire [31:0] rf_core_ctrlport_req_data [0:NUM_DBOARDS-1]; + wire rf_core_ctrlport_resp_ack [0:NUM_DBOARDS-1]; + wire [31:0] rf_core_ctrlport_resp_data [0:NUM_DBOARDS-1]; + wire [ 1:0] rf_core_ctrlport_resp_status [0:NUM_DBOARDS-1]; + // GPIO to CPLD ctrlport interface wire db_to_cpld_ctrlport_req_rd [0:NUM_DBOARDS-1]; wire db_to_cpld_ctrlport_req_wr [0:NUM_DBOARDS-1]; @@ -2162,6 +2172,22 @@ module x4xx ( .version_info (rf_core_version[db_i]) ); end // gen_rf_core_full + + // terminate unused rf core ctrlport interfaces + ctrlport_terminator #( + .START_ADDRESS (0), + .LAST_ADDRESS (2**CTRLPORT_ADDR_W-1) + ) pl_terminator ( + .ctrlport_clk (rfdc_clk[db_i]), + .ctrlport_rst (radio_rst[db_i]), + .s_ctrlport_req_wr (rf_core_ctrlport_req_wr[db_i]), + .s_ctrlport_req_rd (rf_core_ctrlport_req_rd[db_i]), + .s_ctrlport_req_addr (rf_core_ctrlport_req_addr[db_i]), + .s_ctrlport_req_data (rf_core_ctrlport_req_data[db_i]), + .s_ctrlport_resp_ack (rf_core_ctrlport_resp_ack[db_i]), + .s_ctrlport_resp_status (rf_core_ctrlport_resp_status[db_i]), + .s_ctrlport_resp_data (rf_core_ctrlport_resp_data[db_i]) + ); end // gen_rf_cores `ifdef X440 @@ -2975,6 +3001,13 @@ module x4xx ( .m_ctrlport_radio_resp_ack ({ db_ctrlport_resp_ack [1], db_ctrlport_resp_ack [0] }), .m_ctrlport_radio_resp_status ({ db_ctrlport_resp_status [1], db_ctrlport_resp_status [0] }), .m_ctrlport_radio_resp_data ({ db_ctrlport_resp_data [1], db_ctrlport_resp_data [0] }), + .m_ctrlport_rf_core_req_wr ({ rf_core_ctrlport_req_wr [1], rf_core_ctrlport_req_wr [0] }), + .m_ctrlport_rf_core_req_rd ({ rf_core_ctrlport_req_rd [1], rf_core_ctrlport_req_rd [0] }), + .m_ctrlport_rf_core_req_addr ({ rf_core_ctrlport_req_addr [1], rf_core_ctrlport_req_addr [0] }), + .m_ctrlport_rf_core_req_data ({ rf_core_ctrlport_req_data [1], rf_core_ctrlport_req_data [0] }), + .m_ctrlport_rf_core_resp_ack ({ rf_core_ctrlport_resp_ack [1], rf_core_ctrlport_resp_ack [0] }), + .m_ctrlport_rf_core_resp_status({ rf_core_ctrlport_resp_status [1], rf_core_ctrlport_resp_status [0] }), + .m_ctrlport_rf_core_resp_data ({ rf_core_ctrlport_resp_data [1], rf_core_ctrlport_resp_data [0] }), .start_nco_reset (start_nco_reset), .nco_reset_done (nco_reset_done), .adc_reset_pulse (adc_reset_pulse), diff --git a/top/x400/x4xx_core.v b/top/x400/x4xx_core.v index 638dca1..4294c63 100644 --- a/top/x400/x4xx_core.v +++ b/top/x400/x4xx_core.v @@ -326,6 +326,14 @@ module x4xx_core #( input wire [ 2*NUM_DBOARDS-1:0] m_ctrlport_radio_resp_status, input wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_radio_resp_data, + output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_rf_core_req_wr, + output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_rf_core_req_rd, + output wire [ 20*NUM_DBOARDS-1:0] m_ctrlport_rf_core_req_addr, + output wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_rf_core_req_data, + input wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_rf_core_resp_ack, + input wire [ 2*NUM_DBOARDS-1:0] m_ctrlport_rf_core_resp_status, + input wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_rf_core_resp_data, + // RF Reset Control output wire start_nco_reset, input wire nco_reset_done, @@ -501,6 +509,13 @@ module x4xx_core #( .m_radio_ctrlport_resp_ack (m_ctrlport_radio_resp_ack), .m_radio_ctrlport_resp_status (m_ctrlport_radio_resp_status), .m_radio_ctrlport_resp_data (m_ctrlport_radio_resp_data), + .m_rf_core_ctrlport_req_wr (m_ctrlport_rf_core_req_wr), + .m_rf_core_ctrlport_req_rd (m_ctrlport_rf_core_req_rd), + .m_rf_core_ctrlport_req_addr (m_ctrlport_rf_core_req_addr), + .m_rf_core_ctrlport_req_data (m_ctrlport_rf_core_req_data), + .m_rf_core_ctrlport_resp_ack (m_ctrlport_rf_core_resp_ack), + .m_rf_core_ctrlport_resp_status (m_ctrlport_rf_core_resp_status), + .m_rf_core_ctrlport_resp_data (m_ctrlport_rf_core_resp_data), .start_nco_reset (start_nco_reset), .nco_reset_done (nco_reset_done), .adc_reset_pulse (adc_reset_pulse), diff --git a/top/x400/x4xx_core_common.v b/top/x400/x4xx_core_common.v index ca82abd..c816941 100644 --- a/top/x400/x4xx_core_common.v +++ b/top/x400/x4xx_core_common.v @@ -133,6 +133,15 @@ module x4xx_core_common #( input wire [ 2*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_status, input wire [ 32*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_data, + // CtrlPort Master (to RF cores, Domain: radio_clk) + output wire [ 1*NUM_DBOARDS-1:0] m_rf_core_ctrlport_req_wr, + output wire [ 1*NUM_DBOARDS-1:0] m_rf_core_ctrlport_req_rd, + output wire [ 20*NUM_DBOARDS-1:0] m_rf_core_ctrlport_req_addr, + output wire [ 32*NUM_DBOARDS-1:0] m_rf_core_ctrlport_req_data, + input wire [ 1*NUM_DBOARDS-1:0] m_rf_core_ctrlport_resp_ack, + input wire [ 2*NUM_DBOARDS-1:0] m_rf_core_ctrlport_resp_status, + input wire [ 32*NUM_DBOARDS-1:0] m_rf_core_ctrlport_resp_data, + // RF Reset Control output wire start_nco_reset, input wire nco_reset_done, @@ -477,6 +486,7 @@ module x4xx_core_common #( localparam [19:0] DIGITAL_IFC_OFFSET = DIO_WINDOW + DIGITAL_IFC_REGS; // Register space size calculation + localparam [31:0] RF_CORE_WINDOW_SIZE_W = $clog2(RF_CORE_WINDOW_SIZE); localparam [31:0] RFDC_TIMING_WINDOW_SIZE_W = $clog2(RFDC_TIMING_WINDOW_SIZE); localparam [31:0] DB_WINDOW_SIZE_W = $clog2(DB_WINDOW_SIZE); localparam [31:0] DIO_SOURCE_CONTROL_SIZE_W = $clog2(DIO_SOURCE_CONTROL_SIZE); @@ -484,16 +494,18 @@ module x4xx_core_common #( localparam [31:0] DIGITAL_IFC_REGS_SIZE_W = $clog2(DIGITAL_IFC_REGS_SIZE); ctrlport_decoder_param #( - .NUM_SLAVES (5), + .NUM_SLAVES (6), .PORT_BASE ({ DIGITAL_IFC_OFFSET, DIO_SOURCE_CONTROL_OFFSET, RADIO_GPIO_ATR_OFFSET, + RF_CORE_WINDOW[19:0], RFDC_TIMING_WINDOW[19:0], DB_WINDOW[19:0] }), .PORT_ADDR_W ({ DIGITAL_IFC_REGS_SIZE_W, DIO_SOURCE_CONTROL_SIZE_W, RADIO_GPIO_ATR_SIZE_W, + RF_CORE_WINDOW_SIZE_W, RFDC_TIMING_WINDOW_SIZE_W, DB_WINDOW_SIZE_W }) @@ -513,21 +525,25 @@ module x4xx_core_common #( .m_ctrlport_req_wr ({ gpio_spi_ctrlport_req_wr [ 1*db_i+: 1], radio_dio_req_wr [ 1*db_i+: 1], gpio_atr_ctrlport_req_wr [ 1*db_i+: 1], + m_rf_core_ctrlport_req_wr [ 1*db_i+: 1], rf_ctrlport_req_wr [ 1*db_i+: 1], m_radio_ctrlport_req_wr [ 1*db_i+: 1] }), .m_ctrlport_req_rd ({ gpio_spi_ctrlport_req_rd [ 1*db_i+: 1], radio_dio_req_rd [ 1*db_i+: 1], gpio_atr_ctrlport_req_rd [ 1*db_i+: 1], + m_rf_core_ctrlport_req_rd [ 1*db_i+: 1], rf_ctrlport_req_rd [ 1*db_i+: 1], m_radio_ctrlport_req_rd [ 1*db_i+: 1] }), .m_ctrlport_req_addr ({ gpio_spi_ctrlport_req_addr [20*db_i+:20], radio_dio_req_addr [20*db_i+:20], gpio_atr_ctrlport_req_addr [20*db_i+:20], + m_rf_core_ctrlport_req_addr [20*db_i+:20], rf_ctrlport_req_addr [20*db_i+:20], m_radio_ctrlport_req_addr [20*db_i+:20] }), .m_ctrlport_req_data ({ gpio_spi_ctrlport_req_data [32*db_i+:32], radio_dio_req_data [32*db_i+:32], gpio_atr_ctrlport_req_data [32*db_i+:32], + m_rf_core_ctrlport_req_data [32*db_i+:32], rf_ctrlport_req_data [32*db_i+:32], m_radio_ctrlport_req_data [32*db_i+:32] }), .m_ctrlport_req_byte_en (), @@ -536,16 +552,19 @@ module x4xx_core_common #( .m_ctrlport_resp_ack ({ gpio_spi_ctrlport_resp_ack [ 1*db_i+: 1], radio_dio_resp_ack [ 1*db_i+: 1], gpio_atr_ctrlport_resp_ack [ 1*db_i+: 1], + m_rf_core_ctrlport_resp_ack [ 1*db_i+: 1], rf_ctrlport_resp_ack [ 1*db_i+: 1], m_radio_ctrlport_resp_ack [ 1*db_i+: 1] }), .m_ctrlport_resp_status ({ gpio_spi_ctrlport_resp_status [ 2*db_i+: 2], radio_dio_resp_status [ 2*db_i+: 2], gpio_atr_ctrlport_resp_status [ 2*db_i+: 2], + m_rf_core_ctrlport_resp_status [ 2*db_i+: 2], rf_ctrlport_resp_status [ 2*db_i+: 2], m_radio_ctrlport_resp_status [ 2*db_i+: 2] }), .m_ctrlport_resp_data ({ gpio_spi_ctrlport_resp_data [32*db_i+:32], radio_dio_resp_data [32*db_i+:32], gpio_atr_ctrlport_resp_data [32*db_i+:32], + m_rf_core_ctrlport_resp_data [32*db_i+:32], rf_ctrlport_resp_data [32*db_i+:32], m_radio_ctrlport_resp_data [32*db_i+:32] }) ); @@ -891,9 +910,12 @@ endmodule // Daughterboard GPIO interface. Register access within this space // is directed to the associated daughterboard CPLD. // -// +// // RFDC timing control interface. // +// +// Interface for the RF core. +// // // DIO control interface. Interacts with the DIO source selection // block, ATR-based DIO control and the DIO digital interface