fpga: e31x: Change RFNoC Ctrl clock to 40 MHz

Original-commit: 8622a8013a429674de59cbff522b2722c8afa449
2020-08-19 12:28:22 -05:00
parent fd113147be
commit 28955fb9f4
2 changed files with 3 additions and 1 deletions
@@ -849,6 +849,7 @@ module e31x (
    .radio_rst(radio_rst),
    .bus_clk(bus_clk),
    .bus_rst(bus_rst),
+    .clk40(clk40),

    // Clocking and PPS Controls/Indicators
    .pps_refclk(pps),
@@ -34,6 +34,7 @@ module e31x_core #(
  input wire radio_rst,
  input wire bus_clk,
  input wire bus_rst,
+  input wire clk40,

  // Motherboard Registers: AXI lite interface
  input wire                    s_axi_aclk,
@@ -666,7 +667,7 @@ module e31x_core #(
    .PROTOVER(RFNOC_PROTOVER)
  ) rfnoc_image_core_i (
    .chdr_aclk               (bus_clk    ),
-    .ctrl_aclk               (bus_clk    ), //TODO: X310 uses bus_clk_div2. we can also reduce it here.
+    .ctrl_aclk               (clk40      ),
    .core_arst               (bus_rst    ),
    .device_id               (device_id  ),
    .radio_clk               (radio_clk  ),