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fpga: e31x: Change RFNoC Ctrl clock to 40 MHz

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Original-commit: 8622a8013a429674de59cbff522b2722c8afa449
This commit is contained in:
Wade Fife
2020-08-19 12:28:22 -05:00
parent fd113147be
commit 28955fb9f4
2 changed files with 3 additions and 1 deletions
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top/e31x/e31x.v
+1
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@@ -849,6 +849,7 @@ module e31x (
.radio_rst(radio_rst), .radio_rst(radio_rst),
.bus_clk(bus_clk), .bus_clk(bus_clk),
.bus_rst(bus_rst), .bus_rst(bus_rst),
.clk40(clk40),
// Clocking and PPS Controls/Indicators // Clocking and PPS Controls/Indicators
.pps_refclk(pps), .pps_refclk(pps),
top/e31x/e31x_core.v
+2 -1
View File
@@ -34,6 +34,7 @@ module e31x_core #(
input wire radio_rst, input wire radio_rst,
input wire bus_clk, input wire bus_clk,
input wire bus_rst, input wire bus_rst,
input wire clk40,
// Motherboard Registers: AXI lite interface // Motherboard Registers: AXI lite interface
input wire s_axi_aclk, input wire s_axi_aclk,
@@ -666,7 +667,7 @@ module e31x_core #(
.PROTOVER(RFNOC_PROTOVER) .PROTOVER(RFNOC_PROTOVER)
) rfnoc_image_core_i ( ) rfnoc_image_core_i (
.chdr_aclk (bus_clk ), .chdr_aclk (bus_clk ),
.ctrl_aclk (bus_clk ), //TODO: X310 uses bus_clk_div2. we can also reduce it here. .ctrl_aclk (clk40 ),
.core_arst (bus_rst ), .core_arst (bus_rst ),
.device_id (device_id ), .device_id (device_id ),
.radio_clk (radio_clk ), .radio_clk (radio_clk ),