miegl/b210-k7-fpga
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fpga: Fix first arg in calls to $fatal()

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This fixes warnings regarding the first argument to $fatal(), which is
supposed to be a number indicating what diagnostics to display. 1
corresponds to "Prints simulation time and location".


Original-commit: 58763bdfdaa276155ec6b79a3e5420de17172c7a
This commit is contained in:
Wade Fife
2022-06-28 10:34:18 -05:00
parent 03abebec26
commit 287659ddeb
9 changed files with 67 additions and 68 deletions
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lib/axi4s_sv/axi4s_packet_gate.sv
+7 -7
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@@ -35,19 +35,19 @@ module axi4s_packet_gate #(
// Parameter Checks
initial begin
assert (i.DATA_WIDTH == o.DATA_WIDTH) else
$fatal("DATA_WIDTH mismatch");
$fatal(1, "DATA_WIDTH mismatch");
assert (i.USER_WIDTH == o.USER_WIDTH) else
$fatal("USER_WIDTH mismatch");
$fatal(1, "USER_WIDTH mismatch");
assert (i.TDATA == o.TDATA) else
$fatal("TDATA present mismatch");
$fatal(1, "TDATA present mismatch");
assert (i.TUSER == o.TUSER) else
$fatal("TUSER present mismatch");
$fatal(1, "TUSER present mismatch");
assert (i.TKEEP == o.TKEEP) else
$fatal("TKEEP present mismatch");
$fatal(1, "TKEEP present mismatch");
assert (i.TLAST == 1) else
$fatal("i.TLAST not present");
$fatal(1, "i.TLAST not present");
assert (o.TLAST == 1) else
$fatal("o.TLAST not present");
$fatal(1, "o.TLAST not present");
end
localparam WIDTH = i.DWIDTH + i.UWIDTH + i.KWIDTH;