miegl/b210-k7-fpga
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fpga: Fix first arg in calls to $fatal()

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This fixes warnings regarding the first argument to $fatal(), which is
supposed to be a number indicating what diagnostics to display. 1
corresponds to "Prints simulation time and location".


Original-commit: 58763bdfdaa276155ec6b79a3e5420de17172c7a
This commit is contained in:
Wade Fife
2022-06-28 10:34:18 -05:00
parent 03abebec26
commit 287659ddeb
9 changed files with 67 additions and 68 deletions
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lib/axi4s_sv/axi4s_add_bytes.sv
+5 -5
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@@ -57,15 +57,15 @@ module axi4s_add_bytes #(
// Parameter Checks
initial begin
assert (i.DATA_WIDTH == o.DATA_WIDTH) else
$fatal("DATA_WIDTH mismatch");
$fatal(1, "DATA_WIDTH mismatch");
assert (i.USER_WIDTH == o.USER_WIDTH) else
$fatal("USER_WIDTH mismatch");
$fatal(1, "USER_WIDTH mismatch");
assert (i.USER_WIDTH >= UWIDTH) else
$fatal("i.USER_WIDTH is to small");
$fatal(1, "i.USER_WIDTH is to small");
assert (o.USER_WIDTH >= UWIDTH) else
$fatal("o.USER_WIDTH is to small");
$fatal(1, "o.USER_WIDTH is to small");
assert (ADD_START == 0) else
$fatal("Only tested for ADD_START = 0");
$fatal(1, "Only tested for ADD_START = 0");
end
AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),