fpga: rfnoc: Add RFNoC CHDR resize module
Original-commit: a94ea11f00bba2c4227c9ab173eb4b6ef1049bad
This commit is contained in:
Wade Fife
@@ -0,0 +1,448 @@
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//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: chdr_convert_up
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//
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// Description:
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//
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// Takes a CHDR packet data stream that was generated using a CHDR width
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// equal to the current bust width (DATA_W) and reformats the packet stream
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// to use a wider width (O_CHDR_W). It does not resize the bus, but rather
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// only changes the CHDR_W of the encoded packets.
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//
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// The metadata might not be a nice multiple of O_CHDR_W sized words. This
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// module repacks the metadata into the new word size, little-endian ordered,
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// and pads the last metadata word with zeros if necessary.
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//
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// Parameters:
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//
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// DATA_W : The width of the data bus and the input CHDR width for the
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// input data stream on i_chdr.
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// O_CHDR_W : CHDR_W for the output data stream on o_chdr. Must be larger
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// than DATA_W.
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// PIPELINE : Indicates whether to add pipeline stages to the input and/or
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// output. This can be: "NONE", "IN", "OUT", or "INOUT".
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//
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`default_nettype none
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module chdr_convert_up #(
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parameter DATA_W = 64,
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parameter O_CHDR_W = 512,
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parameter PIPELINE = "NONE"
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) (
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input wire clk,
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input wire rst,
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// Input
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input wire [DATA_W-1:0] i_chdr_tdata,
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input wire i_chdr_tlast,
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input wire i_chdr_tvalid,
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output wire i_chdr_tready,
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// Output
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output wire [DATA_W-1:0] o_chdr_tdata,
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output wire o_chdr_tlast,
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output wire o_chdr_tvalid,
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input wire o_chdr_tready
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);
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`include "../core/rfnoc_chdr_utils.vh"
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`include "../core/rfnoc_chdr_internal_utils.vh"
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// Calculate ceiling(N/D)
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`define DIV_CEIL(N,D) (((N)+(D)-1)/(D))
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//---------------------------------------------------------------------------
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// Check Parameters
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//---------------------------------------------------------------------------
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generate
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if (!(
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// Must be up-sizing
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(DATA_W < O_CHDR_W) &&
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// CHDR widths must be valid (at least 64 and powers of 2)
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(DATA_W >= 64) &&
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(O_CHDR_W >= 64) &&
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(2**$clog2(DATA_W) == DATA_W) &&
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(2**$clog2(O_CHDR_W) == O_CHDR_W) &&
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// O_CHDR_W must be a multiple of DATA_W
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(O_CHDR_W % DATA_W == 0)
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)) begin : gen_error
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ERROR__Invalid_CHDR_W_parameters();
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end
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endgenerate
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//---------------------------------------------------------------------------
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// Input Register
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//---------------------------------------------------------------------------
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wire [DATA_W-1:0] i_pipe_tdata;
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wire i_pipe_tlast;
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wire i_pipe_tvalid;
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reg i_pipe_tready;
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if (PIPELINE == "IN" || PIPELINE == "INOUT") begin : gen_in_pipeline
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// Add a pipeline stage
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axi_fifo_flop2 #(
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.WIDTH (1 + DATA_W)
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) axi_fifo_flop2_i (
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.clk (clk),
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.reset (rst),
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.clear (1'b0),
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.i_tdata ({i_chdr_tlast, i_chdr_tdata}),
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.i_tvalid (i_chdr_tvalid),
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.i_tready (i_chdr_tready),
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.o_tdata ({i_pipe_tlast, i_pipe_tdata}),
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.o_tvalid (i_pipe_tvalid),
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.o_tready (i_pipe_tready),
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.space (),
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.occupied ()
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);
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end else begin : gen_no_in_pipeline
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assign i_pipe_tdata = i_chdr_tdata;
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assign i_pipe_tlast = i_chdr_tlast;
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assign i_pipe_tvalid = i_chdr_tvalid;
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assign i_chdr_tready = i_pipe_tready;
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end
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//---------------------------------------------------------------------------
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// Up-size State Machine
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//---------------------------------------------------------------------------
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//
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// This state machine does the translation from the smaller CHDR_W to the
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// larger CHDR_W by updating the header and padding words as needed.
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//
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//---------------------------------------------------------------------------
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// States
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localparam [3:0] ST_HDR = 4'd0; // CHDR header
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localparam [3:0] ST_TS = 4'd1; // CHDR timestamp
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localparam [3:0] ST_HDR_PAD = 4'd2; // CHDR header padding
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localparam [3:0] ST_MDATA = 4'd3; // CHDR metadata words
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localparam [3:0] ST_MDATA_PAD = 4'd4; // CHDR metadata padding
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localparam [3:0] ST_PYLD = 4'd5; // CHDR payload words
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localparam [3:0] ST_MGMT_HDR = 4'd6; // CHDR management header word
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localparam [3:0] ST_MGMT_PYLD = 4'd7; // CHDR management payload words
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localparam [3:0] ST_MGMT_PAD = 4'd8; // CHDR management word padding
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localparam [3:0] ST_LAST_PAD = 4'd9; // Pad the last CHDR word
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reg [3:0] state = ST_HDR;
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// Number of input words per output word
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localparam NUM_WORDS = O_CHDR_W/DATA_W;
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// Determine the number of bits needed to represent a counter to track
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// which CHDR words are valid and which are padding.
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localparam COUNT_W = $clog2(NUM_WORDS);
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// Determine the maximum number DATA_W-sized payload words. The maximum
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// packet size is 2**16-1 bytes, then subtract one word for the smallest
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// possible header and convert that to a number of whole CHDR words.
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localparam NUM_PYLD_WORDS = `DIV_CEIL((2**16-1) - (DATA_W/8), DATA_W/8);
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// Determine the number of bits needed to represent a counter to track which
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// I_DATA_W payload word we are processing.
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localparam PYLD_COUNT_W = $clog2(NUM_PYLD_WORDS + 1);
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// Header info we need to save
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reg [4:0] num_mdata_reg;
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reg [2:0] pkt_type_reg;
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// Counters (number of DATA_W sized words processed on the input)
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reg [ 4:0] mdata_count;
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reg [COUNT_W-1:0] word_count; // Zero based (starts at 0)
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// Shortcuts for CHDR header info
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wire [2:0] pkt_type = chdr_get_pkt_type(i_pipe_tdata[63:0]);
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wire [4:0] num_mdata = chdr_get_num_mdata(i_pipe_tdata[63:0]);
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// Calculate payload length in bytes
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wire [15:0] pyld_len_bytes = chdr_calc_payload_length(DATA_W, i_pipe_tdata[63:0]);
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// Calculate the payload length of a management packet in words (management
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// packets have the same number of payload words, regardless of CHDR width).
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wire [PYLD_COUNT_W-1:0] mgmt_pyld_len = `DIV_CEIL(pyld_len_bytes, DATA_W/8);
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// Determine the number of metadata words for the output packet
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wire [4:0] o_num_mdata = `DIV_CEIL(num_mdata, O_CHDR_W/DATA_W);
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// Generate packet headers with updated NumMData and Length fields
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reg [DATA_W-1:0] new_header;
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always @(*) begin
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// Pass through upper bits unchanged (e.g., timestamp)
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new_header = i_pipe_tdata;
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// Update NumMData
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new_header[63:0] = chdr_set_num_mdata(new_header, o_num_mdata);
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// Update packet length
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new_header[63:0] = chdr_update_length(O_CHDR_W, new_header,
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(pkt_type == CHDR_PKT_TYPE_MGMT) ? mgmt_pyld_len * (O_CHDR_W/8) : pyld_len_bytes);
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end
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reg [DATA_W-1:0] new_mgmt_header;
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always @(*) begin
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// Update the CHDRWidth field in the management header.
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new_mgmt_header = i_pipe_tdata;
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new_mgmt_header[63:0] =
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chdr_mgmt_set_chdr_w(i_pipe_tdata[63:0], chdr_w_to_enum(O_CHDR_W));
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end
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reg [DATA_W-1:0] o_pipe_tdata;
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reg o_pipe_tlast;
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reg o_pipe_tvalid;
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wire o_pipe_tready;
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always @(posedge clk) begin
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if (rst) begin
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state <= ST_HDR;
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mdata_count <= 'bX;
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word_count <= 'bX;
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num_mdata_reg <= 'bX;
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pkt_type_reg <= 'bX;
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end else if (o_pipe_tvalid & o_pipe_tready) begin
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// Default assignment
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word_count <= word_count + 1;
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case (state)
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// ST_HDR: CHDR Header
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ST_HDR: begin
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mdata_count <= 1; // The first metadata word will be word 1
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word_count <= 1; // Word 0 is the current word (header)
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pkt_type_reg <= pkt_type;
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// Save the number of DATA_W sized metadata words
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num_mdata_reg <= num_mdata;
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if (DATA_W == 64) begin
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// When CHDR_W == 64, the timestamp comes after the header.
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if (pkt_type == CHDR_PKT_TYPE_DATA_TS) begin
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state <= ST_TS;
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end else begin
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// O_CHDR_W must be at least 128, so there must be at least one
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// word of header padding.
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state <= ST_HDR_PAD;
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end
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end else begin
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// If DATA_W > 64 then O_CHDR_W must be at least 256, so we know
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// there must be some header padding needed.
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state <= ST_HDR_PAD;
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end
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end
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// ST_TS: Timestamp (DATA_W == 64 only)
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ST_TS: begin
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if (O_CHDR_W > 128) begin
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state <= ST_HDR_PAD;
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end else begin
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if (num_mdata_reg != 0) begin
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state <= ST_MDATA;
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end else begin
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state <= ST_PYLD;
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end
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end
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end
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// ST_HDR_PAD: CHDR header padding to fill out the last O_CHDR_W
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ST_HDR_PAD: begin
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if (word_count == NUM_WORDS-1) begin
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if (num_mdata_reg != 0) begin
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state <= ST_MDATA;
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end else if (pkt_type_reg == CHDR_PKT_TYPE_MGMT) begin
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state <= ST_MGMT_HDR;
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end else begin
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state <= ST_PYLD;
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end
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end
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end
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// ST_MDATA: Metadata words
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ST_MDATA: begin
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mdata_count <= mdata_count + 1;
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if (mdata_count == num_mdata_reg) begin
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// If we've input a multiple of O_CHDR_W, then we're done with
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// metadata. Otherwise, we need to add some padding words.
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if (word_count == NUM_WORDS-1) begin
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if (pkt_type_reg == CHDR_PKT_TYPE_MGMT) begin
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state <= ST_MGMT_HDR;
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end else begin
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state <= ST_PYLD;
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end
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end else begin
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state <= ST_MDATA_PAD;
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end
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end
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end
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// ST_MDATA_PAD: Add metadata padding to fill out the last O_CHDR_W
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ST_MDATA_PAD: begin
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if (word_count == NUM_WORDS-1) begin
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if (pkt_type_reg == CHDR_PKT_TYPE_MGMT) begin
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state <= ST_MGMT_HDR;
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end else begin
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state <= ST_PYLD;
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end
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end
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end
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// ST_PYLD: Payload words
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ST_PYLD: begin
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if (i_pipe_tlast) begin
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// We don't pad data words because unused bytes are not sent or
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// expected on the transport.
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state <= ST_HDR;
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end
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end
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// ST_MGMT_HDR: Management header
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ST_MGMT_HDR: begin
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// Management packets are different from other packet types in that
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// the payload is not serialized. So we need to pad each word to make
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// it a full O_CHDR_W size.
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if (i_pipe_tlast) begin
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state <= ST_LAST_PAD;
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end else begin
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state <= ST_MGMT_PAD;
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end
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end
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// ST_MGMT_PYLD: Management operation words
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ST_MGMT_PYLD: begin
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if (i_pipe_tlast) begin
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state <= ST_LAST_PAD;
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end else begin
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state <= ST_MGMT_PAD;
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end
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end
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// ST_MGMT_PAD: Management word padding
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ST_MGMT_PAD: begin
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if (word_count == NUM_WORDS-1) begin
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state <= ST_MGMT_PYLD;
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end
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end
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// ST_LAST_PAD: Pad the last word so output is a multiple of O_CHDR_W
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ST_LAST_PAD : begin
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if (word_count == NUM_WORDS-1) begin
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state <= ST_HDR;
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end
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end
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endcase
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end
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end
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//-----------------------------
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// State machine output logic
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//-----------------------------
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always @(*) begin
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case (state)
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ST_HDR : begin
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o_pipe_tdata = new_header;
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o_pipe_tvalid = i_pipe_tvalid;
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o_pipe_tlast = i_pipe_tlast;
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i_pipe_tready = o_pipe_tready;
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end
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ST_TS : begin
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o_pipe_tdata = i_pipe_tdata;
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o_pipe_tvalid = i_pipe_tvalid;
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o_pipe_tlast = i_pipe_tlast;
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i_pipe_tready = o_pipe_tready;
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end
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ST_HDR_PAD : begin
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o_pipe_tdata = { DATA_W {1'b0} };
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o_pipe_tvalid = 1'b1;
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o_pipe_tlast = 1'b0;
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i_pipe_tready = 1'b0;
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end
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ST_MDATA : begin
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o_pipe_tdata = i_pipe_tdata;
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o_pipe_tvalid = i_pipe_tvalid;
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o_pipe_tlast = 1'b0;
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i_pipe_tready = o_pipe_tready;
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end
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ST_MDATA_PAD : begin
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o_pipe_tdata = { DATA_W {1'b0} };
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o_pipe_tvalid = 1'b1;
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o_pipe_tlast = 1'b0;
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i_pipe_tready = 1'b0;
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end
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ST_PYLD : begin
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o_pipe_tdata = i_pipe_tdata;
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o_pipe_tvalid = i_pipe_tvalid;
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o_pipe_tlast = i_pipe_tlast;
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i_pipe_tready = o_pipe_tready;
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end
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ST_MGMT_HDR : begin
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o_pipe_tdata = new_mgmt_header;
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o_pipe_tvalid = i_pipe_tvalid;
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o_pipe_tlast = 1'b0;
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i_pipe_tready = o_pipe_tready;
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end
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ST_MGMT_PYLD : begin
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o_pipe_tdata = i_pipe_tdata;
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o_pipe_tvalid = i_pipe_tvalid;
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o_pipe_tlast = 1'b0;
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i_pipe_tready = o_pipe_tready;
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end
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ST_MGMT_PAD : begin
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o_pipe_tdata = { DATA_W {1'b0} };
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o_pipe_tvalid = 1'b1;
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o_pipe_tlast = 1'b0;
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i_pipe_tready = 1'b0;
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end
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ST_LAST_PAD : begin
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o_pipe_tdata = { DATA_W {1'b0} };
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o_pipe_tvalid = 1'b1;
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o_pipe_tlast = (word_count == NUM_WORDS-1);
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i_pipe_tready = 1'b0;
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end
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default : begin
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o_pipe_tdata = 'bX;
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o_pipe_tvalid = 1'bX;
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o_pipe_tlast = 1'bX;
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i_pipe_tready = 1'bX;
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end
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endcase
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end
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//---------------------------------------------------------------------------
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// Output Register
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//---------------------------------------------------------------------------
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if (PIPELINE == "OUT" || PIPELINE == "INOUT") begin : gen_out_pipeline
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// Add a pipeline stage
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axi_fifo_flop2 #(
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.WIDTH (1 + DATA_W)
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) axi_fifo_flop2_i (
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.clk (clk),
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.reset (rst),
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.clear (1'b0),
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.i_tdata ({ o_pipe_tlast, o_pipe_tdata }),
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.i_tvalid (o_pipe_tvalid),
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.i_tready (o_pipe_tready),
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.o_tdata ({ o_chdr_tlast, o_chdr_tdata }),
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.o_tvalid (o_chdr_tvalid),
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.o_tready (o_chdr_tready),
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.space (),
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.occupied ()
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);
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end else begin : gen_no_out_pipeline
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assign o_chdr_tdata = o_pipe_tdata;
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assign o_chdr_tlast = o_pipe_tlast;
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assign o_chdr_tvalid = o_pipe_tvalid;
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assign o_pipe_tready = o_chdr_tready;
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end
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endmodule
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`default_nettype wire
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Block a user