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fpga: lib: Add synthesizable AXI4-Stream SV components

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Components are connected together with AxiStreamIfc. Some features
include:
  (1) Add bytes to the start of a packet
  (2) Remove bytes from a packet
  (3) Wrappers for some older components
      a.  fifo - buffer but imediately pass a packet
      b.  packet_gate - buffer and hold till end of packet
      c.  width_conv - cross clock domains and change width of axi bus

The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can
be used to connect to ports with continuous assignment.
AxiStreamPacketIf must be used procedurally but allows the following
new methods:
  - reached_packet_byte - notify when tdata contains a paritcular byte
  - get_packet_byte/get_packet_field - extract a byte or field from axi
  - put_packet_byte/put_packet_field - overwrite a byte or field onto axi


Original-commit: c3bca6c87700054c96320de119a58f6a688dbd5a
This commit is contained in:
Andrew Moch
2020-06-25 14:44:04 -05:00
committed by Wade Fife
parent 6940db90e3
commit 23be04661f
20 changed files with 4197 additions and 80 deletions
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tools/utils/testbenches.excludes
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@@ -13,3 +13,7 @@ top/n3xx/sim/ten_gig_eth_loopback
top/x300/sim/x300_pcie_int
top/n3xx/dboards/eiscat/radio/noc_block_ddc_eiscat_tb
top/n3xx/dboards/eiscat/radio/noc_block_radio_core_eiscat_tb
# These testbenches only work in ModelSim
lib/axi4s_sv/axi4s_remove_bytes_tb
lib/axi4s_sv/axi4s_add_bytes_tb