fpga: lib: Add synthesizable AXI4-Stream SV components

Components are connected together with AxiStreamIfc. Some features include: (1) Add bytes to the start of a packet (2) Remove bytes from a packet (3) Wrappers for some older components a. fifo - buffer but imediately pass a packet b. packet_gate - buffer and hold till end of packet c. width_conv - cross clock domains and change width of axi bus The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can be used to connect to ports with continuous assignment. AxiStreamPacketIf must be used procedurally but allows the following new methods: - reached_packet_byte - notify when tdata contains a paritcular byte - get_packet_byte/get_packet_field - extract a byte or field from axi - put_packet_byte/put_packet_field - overwrite a byte or field onto axi Original-commit: c3bca6c87700054c96320de119a58f6a688dbd5a
2020-06-25 14:44:04 -05:00
parent 6940db90e3
commit 23be04661f
20 changed files with 4197 additions and 80 deletions
@@ -0,0 +1,82 @@
+//
+// Copyright 2020 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axi4s_fifo
+//
+// Description: System Verilog wrapper for axi_fifo that accepts an
+// AxiStreamIfc with slave_user/master_uer interface.
+//
+// Parameters:
+//   SIZE  - 2**SIZE words are stored
+
+module axi4s_fifo #(
+  int SIZE  = 1 // default size set to one to act as a pipe phase
+ ) (
+  input logic clear=1'b0,
+  interface   i,  // AxiStreamIf or AxiStreamPacketIf
+  interface   o,  // AxiStreamIf or AxiStreamPacketIf
+  output logic [15:0] space,
+  output logic [15:0] occupied
+);
+
+  `include "axi4s.vh"
+  
+  // Parameter Checks
+  initial begin
+    assert (i.DATA_WIDTH == o.DATA_WIDTH) else
+     $fatal("DATA_WIDTH mismatch");
+    assert (i.USER_WIDTH == o.USER_WIDTH) else
+      $fatal("USER_WIDTH mismatch");
+    assert (i.TDATA == o.TDATA) else
+      $fatal("TDATA present mismatch");
+    assert (i.TUSER == o.TUSER) else
+      $fatal("TUSER present mismatch");
+    assert (i.TKEEP == o.TKEEP) else
+      $fatal("TKEEP present mismatch");
+    assert (i.TLAST == o.TLAST) else
+      $fatal("TLAST present mismatch");
+  end
+
+  AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),
+    .TDATA(i.TDATA),.TKEEP(i.TKEEP),.TUSER(i.TUSER),.TLAST(i.TLAST),
+    .MAX_PACKET_BYTES(i.MAX_PACKET_BYTES))
+    s0(i.clk,i.rst);
+  AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),
+    .TDATA(i.TDATA),.TKEEP(i.TKEEP),.TUSER(i.TUSER),.TLAST(i.TLAST),
+    .MAX_PACKET_BYTES(i.MAX_PACKET_BYTES))
+    s1(i.clk,i.rst);
+
+  // move from AxiStreamIfc to AxiStreamPacketIf
+  always_comb begin
+    `AXI4S_ASSIGN(s0,i)
+  end
+  // move from AxiStreamPacketIf to AxiStreamIfc
+  always_comb begin
+    `AXI4S_ASSIGN(o,s1)
+  end
+
+  logic [s0.PACKED_WIDTH-1:0] s0_data;
+  logic [s1.PACKED_WIDTH-1:0] s1_data;
+  always_comb s0_data = s0.pack();
+  always_comb s1.unpack(s1_data);
+
+  logic s0_ready, s1_valid;
+  always_comb s0.tready = s0_ready;
+  always_comb s1.tvalid = s1_valid;
+
+  axi_fifo #(
+    .WIDTH(s0.PACKED_WIDTH),.SIZE(SIZE)
+  ) axi_fifo_i (
+    .clk(s0.clk), .reset(s0.rst), .clear(clear),
+    .i_tdata(s0_data),
+    .i_tvalid(s0.tvalid),
+    .i_tready(s0_ready),
+    .o_tdata(s1_data),
+    .o_tvalid(s1_valid),
+    .o_tready(s1.tready),
+    .space(space), .occupied(occupied)
+  );
+
+endmodule : axi4s_fifo