fpga: lib: Add synthesizable AXI4-Stream SV components
Components are connected together with AxiStreamIfc. Some features
include:
(1) Add bytes to the start of a packet
(2) Remove bytes from a packet
(3) Wrappers for some older components
a. fifo - buffer but imediately pass a packet
b. packet_gate - buffer and hold till end of packet
c. width_conv - cross clock domains and change width of axi bus
The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can
be used to connect to ports with continuous assignment.
AxiStreamPacketIf must be used procedurally but allows the following
new methods:
- reached_packet_byte - notify when tdata contains a paritcular byte
- get_packet_byte/get_packet_field - extract a byte or field from axi
- put_packet_byte/put_packet_field - overwrite a byte or field onto axi
Original-commit: c3bca6c87700054c96320de119a58f6a688dbd5a
This commit is contained in:
Andrew Moch
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#
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# Copyright 2020 Ettus Research, A National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/axi4s_sv/Makefile.srcs
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DESIGN_SRCS = $(abspath \
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$(AXI4S_SV_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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TB_TOP_MODULE = axi4s_add_bytes_all_tb
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SIM_TOP = $(TB_TOP_MODULE)
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SIM_SRCS = \
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$(abspath $(TB_TOP_MODULE).sv )\
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$(abspath axi4s_add_bytes_tb.sv )
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# supressing the following worthless reminder.
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#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
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# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
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SVLOG_ARGS = -suppress 2583
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,53 @@
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//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axi4s_add_bytes_all_tb
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//
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// Description: Testbench for axi_add_bytes
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// Exercise corner cases parameters for adding bytes to the front of a packet
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//
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module axi4s_add_bytes_all_tb;
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// actual use cases
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// Add Ethernet header from a packet includes a preamble
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axi4s_add_bytes_tb #(.TEST_NAME("ENET_64_HADD"),.WIDTH(64),.ADD_START(0),.ADD_BYTES(48))
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ENET_64_HADD48 ();
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axi4s_add_bytes_tb #(.TEST_NAME("ENET_128_HADD"),.WIDTH(128),.ADD_START(0),.ADD_BYTES(48))
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ENET_128_HADD48 ();
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axi4s_add_bytes_tb #(.TEST_NAME("ENET_256_HADD"),.WIDTH(256),.ADD_START(0),.ADD_BYTES(48))
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ENET_256_HADD48 ();
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axi4s_add_bytes_tb #(.TEST_NAME("ENET_512_HADD"),.WIDTH(512),.ADD_START(0),.ADD_BYTES(48))
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ENET_512_HADD48 ();
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// Add Preamble header from a packet
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axi4s_add_bytes_tb #(.TEST_NAME("ENET_64_PADD"),.WIDTH(64),.ADD_START(0),.ADD_BYTES(6))
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ENET_64_PADD6 ();
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axi4s_add_bytes_tb #(.TEST_NAME("ENET_128_PADD"),.WIDTH(128),.ADD_START(0),.ADD_BYTES(6))
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ENET_128_PADD6 ();
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axi4s_add_bytes_tb #(.TEST_NAME("ENET_256_PADD"),.WIDTH(256),.ADD_START(0),.ADD_BYTES(6))
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ENET_256_PADD6 ();
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axi4s_add_bytes_tb #(.TEST_NAME("ENET_512_PADD"),.WIDTH(512),.ADD_START(0),.ADD_BYTES(6))
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ENET_512_PADD6 ();
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// START cases - removal starts at LSB of word
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axi4s_add_bytes_tb #(.TEST_NAME("SSTART_32_0:0"),.WIDTH(32),.ADD_START(0),.ADD_BYTES(1))
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SSTART_32_0to0 ();
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axi4s_add_bytes_tb #(.TEST_NAME("SSTART_32_1:0"),.WIDTH(32),.ADD_START(0),.ADD_BYTES(2))
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SSTART_32_0to1 ();
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axi4s_add_bytes_tb #(.TEST_NAME("SSTART_32_2:0"),.WIDTH(32),.ADD_START(0),.ADD_BYTES(3))
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SSTART_32_0to2 ();
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axi4s_add_bytes_tb #(.TEST_NAME("EXACT_32_3:0"), .WIDTH(32),.ADD_START(0),.ADD_BYTES(4))
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EXACT_32_0to3 ();
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axi4s_add_bytes_tb #(.TEST_NAME("MSTART_32_4:0"),.WIDTH(32),.ADD_START(0),.ADD_BYTES(5))
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MSTART_32_0to4 ();
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axi4s_add_bytes_tb #(.TEST_NAME("MSTART_32_5:0"),.WIDTH(32),.ADD_START(0),.ADD_BYTES(6))
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MSTART_32_0to5 ();
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axi4s_add_bytes_tb #(.TEST_NAME("MSTART_32_6:0"),.WIDTH(32),.ADD_START(0),.ADD_BYTES(7))
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MSTART_32_0to6 ();
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axi4s_add_bytes_tb #(.TEST_NAME("EXACT_32_7:0"), .WIDTH(32),.ADD_START(0),.ADD_BYTES(8))
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EXACT_32_0to7 ();
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endmodule
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@@ -0,0 +1,171 @@
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//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axi4s_add_bytes_tb
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//
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// Description: Testbench for axi_add_bytes
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//
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module axi4s_add_bytes_tb #(
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parameter TEST_NAME = "axi_add_bytes",
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WIDTH=32,ADD_START=0,ADD_BYTES=7
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);
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// Include macros and time declarations for use with PkgTestExec
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// To change the name of the TestExec object being used by the assertion
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// macros, `define TEST_EXEC_OBJ before including this file and `undef it at
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// the end of your testbench. Otherwise, it defaults to the shared object
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// "PkgTestExec::test".
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`define TEST_EXEC_OBJ test
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`include "test_exec.svh"
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import PkgAxiStreamBfm::*;
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import PkgTestExec::*;
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import PkgEthernet::*;
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//---------------------------------------------------------------------------
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// Local Parameters
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//---------------------------------------------------------------------------
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localparam UWIDTH = $clog2((WIDTH/8)+1);
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localparam MAX_PACKET_BYTES = 16*1024;
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//---------------------------------------------------------------------------
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// Clocks
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//---------------------------------------------------------------------------
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bit clk;
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bit reset;
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sim_clock_gen #(.PERIOD(5.0), .AUTOSTART(1))
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clk_gen (.clk(clk), .rst(reset));
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//---------------------------------------------------------------------------
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// Bus Functional Models
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//---------------------------------------------------------------------------
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TestExec test = new();
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AxiStreamIf #(.DATA_WIDTH(WIDTH),.USER_WIDTH(UWIDTH),.TKEEP(0),
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.MAX_PACKET_BYTES(MAX_PACKET_BYTES))
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i (clk, reset);
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AxiStreamIf #(.DATA_WIDTH(WIDTH),.USER_WIDTH(UWIDTH),.TKEEP(0),
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.MAX_PACKET_BYTES(MAX_PACKET_BYTES))
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o (clk, reset);
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// Bus functional model for a axi_stream controller
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AxiStreamBfm #(.DATA_WIDTH(WIDTH),.USER_WIDTH(UWIDTH),.TKEEP(0),
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.MAX_PACKET_BYTES(MAX_PACKET_BYTES))
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axis = new(.master(i), .slave(o));
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//----------------------------------------------------
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// Instantiate DUT
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//----------------------------------------------------
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axi4s_add_bytes #(.ADD_START(ADD_START),.ADD_BYTES(ADD_BYTES))
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DUT (.*);
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//---------------------------------------------------------------------------
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// Reset
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//---------------------------------------------------------------------------
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task test_reset();
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test.start_test("Wait for Reset", 10us);
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clk_gen.reset();
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wait(!reset);
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repeat (10) @(posedge clk);
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test.end_test();
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endtask : test_reset
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//---------------------------------------------------------------------------
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// Ethernet to CPU test
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//---------------------------------------------------------------------------
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typedef AxiStreamPacket #(WIDTH, UWIDTH) AxisPacket_t;
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typedef XportStreamPacket #(WIDTH) XportPacket_t;
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task test_samples(int num_samples);
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raw_pkt_t raw;
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localparam PKTS_TO_SEND = 10;
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automatic XportPacket_t send[$];
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automatic XportPacket_t expected[$];
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test.start_test({TEST_NAME,"::Remove Bytes"}, 10us);
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for (int i= 0 ; i < PKTS_TO_SEND; i++) begin
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expected[i] = new;
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send[i] = new;
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get_ramp_raw_pkt(.num_samps(num_samples),.ramp_start((i*num_samples)%256),.ramp_inc(1),.pkt(raw),.SWIDTH(8));
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send[i].push_bytes(raw);
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// Add the bytes to the raw packet to build expected.
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for (int i = 0 ; i < ADD_BYTES; ++i) begin
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raw.insert(ADD_START,0);
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end
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expected[i].push_bytes(raw);
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send[i].tkeep_to_tuser(.ERROR_PROB(10));
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expected[i].tkeep_to_tuser();
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if (send[i].has_error()) expected[i].set_error();
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end
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fork
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begin // Send Thread
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foreach(send[i])begin
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axis.put(send[i]);
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end
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end
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begin // Expected Thread
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foreach(expected[i]) begin
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automatic string str;
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automatic AxisPacket_t actual_a = new();
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automatic XportPacket_t actual = new();
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axis.get(actual_a);
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actual.import_axis(actual_a);
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actual.tuser_to_tkeep();
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str = $sformatf("ADD_START=%3d ADD_BYTES=%3d",ADD_START,ADD_BYTES);
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`ASSERT_ERROR(!actual.compare_w_error(expected[i]),str);
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end
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end
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join
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test.end_test();
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endtask : test_samples
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//----------------------------------------------------
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// Main test loop
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//----------------------------------------------------
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initial begin : tb_main
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integer min_length;
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test.tb_name = TEST_NAME;
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min_length = ADD_START+1;
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axis.run();
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test_reset();
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// Test with default holdoff.
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for (int i=1 ; i < (WIDTH/8)*3 ; ++i) begin
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test_samples(min_length+i);
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end
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// repeat back to back
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axis.set_slave_stall_prob(0);
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axis.set_master_stall_prob(0);
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for (int i=1 ; i < (WIDTH/8)*3 ; ++i) begin
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test_samples(min_length+i);
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end
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// End the TB, but don't $finish, since we don't want to kill other
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// instances of this testbench that may be running.
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test.end_tb(0);
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// Kill the clocks to end this instance of the testbench
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clk_gen.kill();
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end // initial begin
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endmodule
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`undef TEST_EXEC_OBJ
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