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fpga: e31x: Update DRAM IP simulation

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Update the simulation to use the renamed IP.
Add ModelSim support.


Original-commit: c0015db3ea80117e8c66966e55f337e4fe8d29c2
This commit is contained in:
Wade Fife
2022-03-23 08:55:36 -05:00
parent b2684c42a7
commit 1dd8058c08
1 changed files with 22 additions and 4 deletions
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top/e31x/sim/dram_test/Makefile
+22 -4
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@@ -37,12 +37,30 @@ IP_DIR = ../../ip
# Include makefiles and sources for all IP components # Include makefiles and sources for all IP components
# *after* defining the IP_DIR # *after* defining the IP_DIR
include $(IP_DIR)/mig_7series_0/Makefile.inc include $(IP_DIR)/ddr3_16bit/Makefile.inc
DESIGN_SRCS += $(abspath \ DESIGN_SRCS += $(abspath \
$(IP_MIG_7SERIES_0_SRCS) \ $(IP_DDR3_16BIT_SRCS) \
) )
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/ddr3_16bit/ddr3_16bit/user_design/rtl/ddr3_16bit.v \
$(IP_BUILD_DIR)/ddr3_16bit/ddr3_16bit/user_design/rtl/ddr3_16bit_mig_sim.v \
$(IP_BUILD_DIR)/ddr3_16bit/ddr3_16bit/user_design/rtl/*/*.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
secureip \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
MODELSIM_ARGS = glbl -t 1fs
#------------------------------------------------- #-------------------------------------------------
# Testbench Specific # Testbench Specific
#------------------------------------------------- #-------------------------------------------------
@@ -51,8 +69,8 @@ SIM_TOP = dram_test_tb
SIM_SRCS = \ SIM_SRCS = \
$(abspath dram_test_tb.sv) \ $(abspath dram_test_tb.sv) \
$(IP_MIG_7SERIES_0_SIM_OUTS) \ $(IP_DDR3_16BIT_SIM_OUTS) \
$(IP_MIG_7SERIES_TG_SRCS) \ $(IP_DDR3_16BIT_TG_SRCS) \
$(SIM_GENERAL_SRCS) \ $(SIM_GENERAL_SRCS) \
$(SIM_AXI_SRCS) $(SIM_AXI_SRCS)