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fpga: n3xx: Cleanup MTU parameters

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Original-commit: 9e4c8cbbbb8677eecbab66ab01a02375664ad4a2
This commit is contained in:
Wade Fife
2022-09-01 14:41:55 -05:00
parent 521c7684fc
commit 1d9a3018db
5 changed files with 26 additions and 1 deletions
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top/n3xx/dboards/mg/n3xx.v
+8
View File
@@ -331,6 +331,9 @@ module n3xx (
CHDR_W_must_be_64_for_this_USRP();
end
// Log base 2 of the maximum transmission unit (MTU) in bytes
localparam BYTE_MTU = $clog2(8192);
localparam N_AXILITE_SLAVES = 4;
localparam REG_AWIDTH = 14; // log2(0x4000)
localparam QSFP_REG_AWIDTH = 17; // log2(0x20000)
@@ -1179,6 +1182,7 @@ module n3xx (
.PORTNUM_BASE (4),
.REG_DWIDTH (REG_DWIDTH),
.REG_AWIDTH (QSFP_REG_AWIDTH),
.BYTE_MTU (BYTE_MTU),
.RFNOC_PROTOVER (RFNOC_PROTOVER),
.NODE_INST_BASE (0)
) qsfp_wrapper_i (
@@ -1697,6 +1701,7 @@ module n3xx (
.REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
.REG_AWIDTH(REG_AWIDTH), // Width of the address bus
.PORTNUM_BASE(8'd0),
.BYTE_MTU(BYTE_MTU),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST_BASE(0)
) sfp_wrapper_0 (
@@ -1870,6 +1875,7 @@ module n3xx (
.REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
.REG_AWIDTH(REG_AWIDTH), // Width of the address bus
.PORTNUM_BASE(8'd1),
.BYTE_MTU(BYTE_MTU),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST_BASE(1)
) sfp_wrapper_1 (
@@ -2583,6 +2589,7 @@ module n3xx (
.DWIDTH(REG_DWIDTH),
.AWIDTH(REG_AWIDTH),
.PORTNUM(8'd1),
.BYTE_MTU(BYTE_MTU),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST(2)
) eth_internal_i (
@@ -3551,6 +3558,7 @@ module n3xx (
.NUM_CHANNELS(NUM_CHANNELS),
.NUM_DBOARDS(NUM_DBOARDS),
.CHDR_W(CHDR_W),
.BYTE_MTU(BYTE_MTU),
.RFNOC_PROTOVER(RFNOC_PROTOVER)
) n3xx_core(
// Clocks and resets
top/n3xx/dboards/rh/n3xx.v
+8
View File
@@ -323,6 +323,9 @@ module n3xx (
CHDR_W_must_be_64_for_this_USRP();
end
// Log base 2 of the maximum transmission unit (MTU) in bytes
localparam BYTE_MTU = $clog2(8192);
localparam N_AXILITE_SLAVES = 4;
localparam REG_AWIDTH = 14; // log2(0x4000)
localparam QSFP_REG_AWIDTH = 17; // log2(0x20000)
@@ -1169,6 +1172,7 @@ module n3xx (
.PORTNUM_BASE (4),
.REG_DWIDTH (REG_DWIDTH),
.REG_AWIDTH (QSFP_REG_AWIDTH),
.BYTE_MTU (BYTE_MTU),
.RFNOC_PROTOVER (RFNOC_PROTOVER),
.NODE_INST_BASE (0)
) qsfp_wrapper_i (
@@ -1688,6 +1692,7 @@ module n3xx (
.REG_AWIDTH(REG_AWIDTH), // Width of the address bus
.GT_COMMON(1),
.PORTNUM_BASE(8'd0),
.BYTE_MTU(BYTE_MTU),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST_BASE(0)
) sfp_wrapper_0 (
@@ -1861,6 +1866,7 @@ module n3xx (
.REG_AWIDTH(REG_AWIDTH), // Width of the address bus
.GT_COMMON(1),
.PORTNUM_BASE(8'd1),
.BYTE_MTU(BYTE_MTU),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST_BASE(1)
) sfp_wrapper_1 (
@@ -2574,6 +2580,7 @@ module n3xx (
.DWIDTH(REG_DWIDTH),
.AWIDTH(REG_AWIDTH),
.PORTNUM(8'd1),
.BYTE_MTU(BYTE_MTU),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
.NODE_INST(2)
) eth_internal_i (
@@ -3471,6 +3478,7 @@ module n3xx (
.NUM_SPI_PER_DBOARD(4),
.USE_CORRECTION(1),
.CHDR_W(CHDR_W),
.BYTE_MTU(BYTE_MTU),
.RFNOC_PROTOVER(RFNOC_PROTOVER)
) n3xx_core(
// Clocks and resets
top/n3xx/n3xx_core.v
+2
View File
@@ -26,6 +26,7 @@ module n3xx_core #(
parameter USE_CORRECTION = 0,
parameter FP_GPIO_WIDTH = 12, // Front panel GPIO width
parameter CHDR_W = 64,
parameter BYTE_MTU = $clog2(8192),
parameter RFNOC_PROTOVER = {8'd1, 8'd0}
)(
// Clocks and resets
@@ -1118,6 +1119,7 @@ module n3xx_core #(
rfnoc_image_core #(
.CHDR_W (CHDR_W),
.MTU (BYTE_MTU - $clog2(CHDR_W/8)),
.PROTOVER (RFNOC_PROTOVER)
) rfnoc_sandbox_i (
.chdr_aclk (bus_clk ),
top/n3xx/n3xx_mgt_channel_wrapper.v
+3
View File
@@ -21,6 +21,7 @@
// REG_DWIDTH : Width of regport address bus
// REG_AWIDTH : Width of regport data bus
// GT_COMMON : Use GT Common ports on MGT
// BYTE_MTU : Log base 2 of the MTU size in bytes
// RFNOC_PROTOVER : RFNoC protocol version to be reported by transport
// adapters.
// NODE_INST : RFNoC transport adapter node instance for this port
@@ -37,6 +38,7 @@ module n3xx_mgt_channel_wrapper #(
parameter REG_DWIDTH = 32,
parameter REG_AWIDTH = 14,
parameter GT_COMMON = 1,
parameter BYTE_MTU = $clog2(8192),
parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0},
parameter NODE_INST_BASE = 0
)(
@@ -292,6 +294,7 @@ module n3xx_mgt_channel_wrapper #(
.GT_COMMON (GT_COMMON),
.MDIO_EN (MDIO_EN),
.MDIO_PHYADDR (MDIO_PHYADDR),
.BYTE_MTU (BYTE_MTU),
.RFNOC_PROTOVER (RFNOC_PROTOVER),
.PORTNUM (PORTNUM_BASE + l),
.NODE_INST (NODE_INST_BASE + l)
top/n3xx/n3xx_mgt_wrapper.v
+5 -1
View File
@@ -19,6 +19,7 @@
// PORTNUM : Port number
// MDIO_EN : Enables internal MDIO master
// MDIO_PHYADDR : Address to use for the MDIO
// BYTE_MTU : Log base 2 of the MTU size in bytes
// RFNOC_PROTOVER : RFNoC protocol version to be reported by transport
// adapters.
// NODE_INST : RFNoC transport adapter node instance for this port
@@ -38,6 +39,7 @@ module n3xx_mgt_wrapper #(
parameter [ 7:0] PORTNUM = 8'd0,
parameter MDIO_EN = 0,
parameter [ 4:0] MDIO_PHYADDR = 5'd0,
parameter BYTE_MTU = $clog2(8192),
parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0},
parameter NODE_INST = 0,
parameter EN_RX_KV_MAP_CFG = 1,
@@ -423,6 +425,8 @@ module n3xx_mgt_wrapper #(
if (EN_RX_KV_MAP_CFG || EN_RX_RAW_PYLD) begin : gen_eth_ipv4_interface_wrapper
eth_ipv4_interface_wrapper #(
.PROTOVER (RFNOC_PROTOVER),
.CPU_FIFO_SIZE (BYTE_MTU),
.CHDR_FIFO_SIZE (BYTE_MTU),
.NODE_INST (NODE_INST),
.REG_AWIDTH (REG_AWIDTH),
.BASE (REG_BASE_ETH_SWITCH),
@@ -482,7 +486,7 @@ module n3xx_mgt_wrapper #(
else begin : gen_eth_interface
eth_interface #(
.PROTOVER (RFNOC_PROTOVER),
.MTU (10),
.MTU (BYTE_MTU-3), // Log base 2 of the MTU in 64-bit words
.NODE_INST (NODE_INST),
.REG_AWIDTH (REG_AWIDTH),
.BASE (REG_BASE_ETH_SWITCH)