fpga: n3xx: Cleanup MTU parameters

Original-commit: 9e4c8cbbbb8677eecbab66ab01a02375664ad4a2

top/n3xx/dboards/mg/n3xx.v

@@ -331,6 +331,9 @@ module n3xx (
     CHDR_W_must_be_64_for_this_USRP();
   end
 
+  // Log base 2 of the maximum transmission unit (MTU) in bytes
+  localparam BYTE_MTU = $clog2(8192);
+
   localparam N_AXILITE_SLAVES = 4;
   localparam REG_AWIDTH = 14; // log2(0x4000)
   localparam QSFP_REG_AWIDTH = 17; // log2(0x20000)
@@ -1179,6 +1182,7 @@ module n3xx (
     .PORTNUM_BASE   (4),
     .REG_DWIDTH     (REG_DWIDTH),
     .REG_AWIDTH     (QSFP_REG_AWIDTH),
+    .BYTE_MTU       (BYTE_MTU),
     .RFNOC_PROTOVER (RFNOC_PROTOVER),
     .NODE_INST_BASE (0)
   ) qsfp_wrapper_i (
@@ -1697,6 +1701,7 @@ module n3xx (
     .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
     .REG_AWIDTH(REG_AWIDTH), // Width of the address bus
     .PORTNUM_BASE(8'd0),
+    .BYTE_MTU(BYTE_MTU),
     .RFNOC_PROTOVER(RFNOC_PROTOVER),
     .NODE_INST_BASE(0)
   ) sfp_wrapper_0 (
@@ -1870,6 +1875,7 @@ module n3xx (
     .REG_DWIDTH(REG_DWIDTH),     // Width of the AXI4-Lite data bus (must be 32 or 64)
     .REG_AWIDTH(REG_AWIDTH),     // Width of the address bus
     .PORTNUM_BASE(8'd1),
+    .BYTE_MTU(BYTE_MTU),
     .RFNOC_PROTOVER(RFNOC_PROTOVER),
     .NODE_INST_BASE(1)
    ) sfp_wrapper_1 (
@@ -2583,6 +2589,7 @@ module n3xx (
     .DWIDTH(REG_DWIDTH),
     .AWIDTH(REG_AWIDTH),
     .PORTNUM(8'd1),
+    .BYTE_MTU(BYTE_MTU),
     .RFNOC_PROTOVER(RFNOC_PROTOVER),
     .NODE_INST(2)
   ) eth_internal_i (
@@ -3551,6 +3558,7 @@ module n3xx (
     .NUM_CHANNELS(NUM_CHANNELS),
     .NUM_DBOARDS(NUM_DBOARDS),
     .CHDR_W(CHDR_W),
+    .BYTE_MTU(BYTE_MTU),
     .RFNOC_PROTOVER(RFNOC_PROTOVER)
   ) n3xx_core(
     // Clocks and resets