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fpga: x400: Expand PS GPIO port for DIO control

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Original-commit: 4bfbb9eeec92fdd3e9d7096006f63477d4848f76
This commit is contained in:
Javier Valenzuela
2022-01-25 10:18:47 -07:00
committed by Wade Fife
parent 5237e5778c
commit 1ac4909e6f
7 changed files with 58 additions and 19 deletions
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top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf
+1 -1
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@@ -854,7 +854,7 @@ set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../../lib/control/r
set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/ram_2port.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/ram_2port.v
set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/handshake.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/handshake.v
set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/pulse_synchronizer.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/pulse_synchronizer.v
set_global_assignment -name VERILOG_FILE ../ctrlport_window.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_window.v
set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys
set_global_assignment -name QSYS_FILE ../ip/osc/osc.qsys set_global_assignment -name QSYS_FILE ../ip/osc/osc.qsys
top/x400/doc/X4XX_FPGA_right.htm
+4 -4
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@@ -24092,9 +24092,9 @@ FPGA version.<BR/>
<tr valign="top"> <tr valign="top">
<td class='value'>4</td> <td class='value'>5</td>
<td class='l'>0x00000004</td> <td class='l'>0x00000005</td>
<td class="l" style="text-align: left;"> <td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p> <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
@@ -24131,9 +24131,9 @@ FPGA version.<BR/>
<tr valign="top"> <tr valign="top">
<td class='value'>554243347</td> <td class='value'>554766864</td>
<td class='l'>0x21091513</td> <td class='l'>0x21111210</td>
<td class="l" style="text-align: left;"> <td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p> <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p>
top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd
+4 -4
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@@ -3,7 +3,7 @@
-- File: x4xx_ps_rfdc_bd.vhd -- File: x4xx_ps_rfdc_bd.vhd
-- Author: niBlockDesign::niBdExportStub -- Author: niBlockDesign::niBdExportStub
-- Original Project: HwBuildTools -- Original Project: HwBuildTools
-- Date: 03 February 2021 -- Date: 27 September 2021
-- --
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
-- (c) Copyright National Instruments Corporation -- (c) Copyright National Instruments Corporation
@@ -226,9 +226,9 @@ port (
dac0_clk_clk_p : in STD_LOGIC; dac0_clk_clk_p : in STD_LOGIC;
dac1_clk_clk_n : in STD_LOGIC; dac1_clk_clk_n : in STD_LOGIC;
dac1_clk_clk_p : in STD_LOGIC; dac1_clk_clk_p : in STD_LOGIC;
gpio_0_tri_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); gpio_0_tri_i : in STD_LOGIC_VECTOR ( 63 downto 0 );
gpio_0_tri_o : out STD_LOGIC_VECTOR ( 31 downto 0 ); gpio_0_tri_o : out STD_LOGIC_VECTOR ( 63 downto 0 );
gpio_0_tri_t : out STD_LOGIC_VECTOR ( 31 downto 0 ); gpio_0_tri_t : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_eth_internal_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); m_axi_eth_internal_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_eth_internal_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_eth_internal_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_eth_internal_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_eth_internal_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl
+2 -2
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@@ -2509,9 +2509,9 @@ proc create_hier_cell_ps { parentCell nameHier } {
CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__GPIO_EMIO_WIDTH {32} \ CONFIG.PSU__GPIO_EMIO_WIDTH {64} \
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {32} \ CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {64} \
CONFIG.PSU__GPIO_EMIO__WIDTH {[91:0]} \ CONFIG.PSU__GPIO_EMIO__WIDTH {[91:0]} \
CONFIG.PSU__GPU_PP0__POWER__ON {0} \ CONFIG.PSU__GPU_PP0__POWER__ON {0} \
CONFIG.PSU__GPU_PP1__POWER__ON {0} \ CONFIG.PSU__GPU_PP1__POWER__ON {0} \
top/x400/regmap/versioning_regs_regmap_utils.vh
+2 -2
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@@ -82,10 +82,10 @@
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MINOR = 'h4; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR localparam FPGA_CURRENT_VERSION_MINOR = 'h5; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h21091513; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h21111210; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_100M_VERSION // Enumerated type RF_CORE_100M_VERSION
localparam RF_CORE_100M_VERSION_SIZE = 7; localparam RF_CORE_100M_VERSION_SIZE = 7;
top/x400/x4xx.v
+32 -6
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@@ -557,8 +557,9 @@ module x4xx (
wire [3:0] eth0_link_up, eth0_activity; wire [3:0] eth0_link_up, eth0_activity;
wire [3:0] eth1_link_up, eth1_activity; wire [3:0] eth1_link_up, eth1_activity;
wire [31:0] gpio_0_tri_i; wire [63:0] gpio_0_tri_i;
wire [31:0] gpio_0_tri_o; wire [63:0] gpio_0_tri_o;
wire [63:0] gpio_0_tri_t;
// RFDC AXI4-Stream interfaces // RFDC AXI4-Stream interfaces
// //
@@ -707,8 +708,20 @@ module x4xx (
assign pl_ps_irq1[6] = eth1_rx_irq[0] || eth1_rx_irq[1] || eth1_rx_irq[2] || eth1_rx_irq[3]; assign pl_ps_irq1[6] = eth1_rx_irq[0] || eth1_rx_irq[1] || eth1_rx_irq[2] || eth1_rx_irq[3];
assign pl_ps_irq1[7] = eth1_tx_irq[0] || eth1_tx_irq[1] || eth1_tx_irq[2] || eth1_tx_irq[3]; assign pl_ps_irq1[7] = eth1_tx_irq[0] || eth1_tx_irq[1] || eth1_tx_irq[2] || eth1_tx_irq[3];
// GPIO inputs (assigned from 31 decreasing) // BD DIO signals
wire [11:0] ps_gpio_out_a;
wire [11:0] ps_gpio_in_a;
wire [11:0] ps_gpio_ddr_a;
wire [11:0] ps_gpio_out_b;
wire [11:0] ps_gpio_in_b;
wire [11:0] ps_gpio_ddr_b;
// GPIO inputs (assigned from 63 decreasing)
// //
// DIO Control
assign gpio_0_tri_i[63:56] = 8'b0;
assign gpio_0_tri_i[55:44] = ps_gpio_in_b;
assign gpio_0_tri_i[43:32] = ps_gpio_in_a;
// Make the current PPS signal available to the PS. // Make the current PPS signal available to the PS.
assign gpio_0_tri_i[31] = pps_refclk; assign gpio_0_tri_i[31] = pps_refclk;
assign gpio_0_tri_i[30] = 0; //unused assign gpio_0_tri_i[30] = 0; //unused
@@ -738,6 +751,13 @@ module x4xx (
// Drive the CPLD JTAG enable line (active high) with GPIO[1] from the PS. // Drive the CPLD JTAG enable line (active high) with GPIO[1] from the PS.
assign PL_CPLD_JTAGEN = gpio_0_tri_o[1]; assign PL_CPLD_JTAGEN = gpio_0_tri_o[1];
// propagate db GPIO direction and output control
assign ps_gpio_ddr_a = gpio_0_tri_t[43:32];
assign ps_gpio_out_a = gpio_0_tri_o[43:32];
assign ps_gpio_ddr_b = gpio_0_tri_t[55:44];
assign ps_gpio_out_b = gpio_0_tri_o[55:44];
x4xx_ps_rfdc_bd x4xx_ps_rfdc_bd_i ( x4xx_ps_rfdc_bd x4xx_ps_rfdc_bd_i (
.adc_data_out_resetn_dclk (adc_data_out_resetn_dclk), .adc_data_out_resetn_dclk (adc_data_out_resetn_dclk),
.adc_enable_data_rclk (adc_enable_data_rclk), .adc_enable_data_rclk (adc_enable_data_rclk),
@@ -943,7 +963,7 @@ module x4xx (
.dac1_clk_clk_p (DAC_CLK_P[1]), .dac1_clk_clk_p (DAC_CLK_P[1]),
.gpio_0_tri_i (gpio_0_tri_i), .gpio_0_tri_i (gpio_0_tri_i),
.gpio_0_tri_o (gpio_0_tri_o), .gpio_0_tri_o (gpio_0_tri_o),
.gpio_0_tri_t (), .gpio_0_tri_t (gpio_0_tri_t),
.m_axi_eth_internal_awaddr (axi_eth_internal_awaddr), .m_axi_eth_internal_awaddr (axi_eth_internal_awaddr),
.m_axi_eth_internal_awprot (), .m_axi_eth_internal_awprot (),
.m_axi_eth_internal_awvalid (axi_eth_internal_awvalid), .m_axi_eth_internal_awvalid (axi_eth_internal_awvalid),
@@ -2099,6 +2119,12 @@ module x4xx (
.gpio_out_b (gpio_out_b), .gpio_out_b (gpio_out_b),
.gpio_en_a (gpio_en_a), .gpio_en_a (gpio_en_a),
.gpio_en_b (gpio_en_b), .gpio_en_b (gpio_en_b),
.ps_gpio_out_a (ps_gpio_out_a),
.ps_gpio_in_a (ps_gpio_in_a),
.ps_gpio_ddr_a (ps_gpio_ddr_a),
.ps_gpio_out_b (ps_gpio_out_b),
.ps_gpio_in_b (ps_gpio_in_b),
.ps_gpio_ddr_b (ps_gpio_ddr_b),
.qsfp_port_0_0_info (qsfp_port_0_0_info), .qsfp_port_0_0_info (qsfp_port_0_0_info),
.qsfp_port_0_1_info (qsfp_port_0_1_info), .qsfp_port_0_1_info (qsfp_port_0_1_info),
.qsfp_port_0_2_info (qsfp_port_0_2_info), .qsfp_port_0_2_info (qsfp_port_0_2_info),
@@ -2220,12 +2246,12 @@ endmodule
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED // <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
// </info> // </info>
// <value name="FPGA_CURRENT_VERSION_MAJOR" integer="7"/> // <value name="FPGA_CURRENT_VERSION_MAJOR" integer="7"/>
// <value name="FPGA_CURRENT_VERSION_MINOR" integer="4"/> // <value name="FPGA_CURRENT_VERSION_MINOR" integer="5"/>
// <value name="FPGA_CURRENT_VERSION_BUILD" integer="0"/> // <value name="FPGA_CURRENT_VERSION_BUILD" integer="0"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="7"/> // <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="7"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/> // <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/> // <value name="FPGA_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
// <value name="FPGA_VERSION_LAST_MODIFIED_TIME" integer="0x21091513"/> // <value name="FPGA_VERSION_LAST_MODIFIED_TIME" integer="0x21111210"/>
// </enumeratedtype> // </enumeratedtype>
// </group> // </group>
//</regmap> //</regmap>
top/x400/x4xx_core.v
+13
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@@ -117,6 +117,13 @@ module x4xx_core #(
input wire [11:0] gpio_in_b, input wire [11:0] gpio_in_b,
output wire [11:0] gpio_out_a, output wire [11:0] gpio_out_a,
output wire [11:0] gpio_out_b, output wire [11:0] gpio_out_b,
// PS GPIO Control
input wire [11:0] ps_gpio_out_a,
output wire [11:0] ps_gpio_in_a,
input wire [11:0] ps_gpio_ddr_a,
input wire [11:0] ps_gpio_out_b,
output wire [11:0] ps_gpio_in_b,
input wire [11:0] ps_gpio_ddr_b,
// Misc // Misc
input [31:0] qsfp_port_0_0_info, input [31:0] qsfp_port_0_0_info,
@@ -294,6 +301,12 @@ module x4xx_core #(
.gpio_in_fabric_b (), .gpio_in_fabric_b (),
.gpio_out_fabric_a (12'b0), .gpio_out_fabric_a (12'b0),
.gpio_out_fabric_b (12'b0), .gpio_out_fabric_b (12'b0),
.ps_gpio_out_a (ps_gpio_out_a),
.ps_gpio_in_a (ps_gpio_in_a),
.ps_gpio_ddr_a (ps_gpio_ddr_a),
.ps_gpio_out_b (ps_gpio_out_b),
.ps_gpio_in_b (ps_gpio_in_b),
.ps_gpio_ddr_b (ps_gpio_ddr_b),
.s_radio_ctrlport_req_wr (ctrlport_radio_req_wr), .s_radio_ctrlport_req_wr (ctrlport_radio_req_wr),
.s_radio_ctrlport_req_rd (ctrlport_radio_req_rd), .s_radio_ctrlport_req_rd (ctrlport_radio_req_rd),
.s_radio_ctrlport_req_addr (ctrlport_radio_req_addr), .s_radio_ctrlport_req_addr (ctrlport_radio_req_addr),