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fpga: x400: Expand PS GPIO port for DIO control

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Original-commit: 4bfbb9eeec92fdd3e9d7096006f63477d4848f76
This commit is contained in:
Javier Valenzuela
2022-01-25 10:18:47 -07:00
committed by Wade Fife
parent 5237e5778c
commit 1ac4909e6f
7 changed files with 58 additions and 19 deletions
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top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd
+4 -4
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@@ -3,7 +3,7 @@
-- File: x4xx_ps_rfdc_bd.vhd
-- Author: niBlockDesign::niBdExportStub
-- Original Project: HwBuildTools
-- Date: 03 February 2021
-- Date: 27 September 2021
--
------------------------------------------------------------------------------------------
-- (c) Copyright National Instruments Corporation
@@ -226,9 +226,9 @@ port (
dac0_clk_clk_p : in STD_LOGIC;
dac1_clk_clk_n : in STD_LOGIC;
dac1_clk_clk_p : in STD_LOGIC;
gpio_0_tri_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_0_tri_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_0_tri_t : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_0_tri_i : in STD_LOGIC_VECTOR ( 63 downto 0 );
gpio_0_tri_o : out STD_LOGIC_VECTOR ( 63 downto 0 );
gpio_0_tri_t : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_eth_internal_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_eth_internal_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_eth_internal_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl
+2 -2
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@@ -2509,9 +2509,9 @@ proc create_hier_cell_ps { parentCell nameHier } {
CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__GPIO_EMIO_WIDTH {32} \
CONFIG.PSU__GPIO_EMIO_WIDTH {64} \
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {32} \
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {64} \
CONFIG.PSU__GPIO_EMIO__WIDTH {[91:0]} \
CONFIG.PSU__GPU_PP0__POWER__ON {0} \
CONFIG.PSU__GPU_PP1__POWER__ON {0} \