fpga: tools: Fix VIVADO_PROJECT variable

Original-commit: 44e7651feee257319dff00577920fe5771473d62

tools/make/viv_design_builder.mak

@@ -25,7 +25,7 @@ BUILD_VIVADO_DESIGN = \
 	export VIV_TOP_MODULE=$(2); \
 	export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
 	export VIV_MODE=$(VIVADO_MODE); \
-	export VIV_SAVE=$(VIVADO_SAVE); \
+	export VIV_PROJECT=$(VIVADO_PROJECT); \
 	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
 	export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
 	export VIV_INCR_BUILD=$(INCR_BUILD); \

tools/scripts/viv_utils.tcl

@@ -26,7 +26,7 @@ namespace eval ::vivado_utils {
     variable g_output_dir   $::env(VIV_OUTPUT_DIR)
     variable g_source_files $::env(VIV_DESIGN_SRCS)
     variable g_vivado_mode  $::env(VIV_MODE)
-    variable g_project_save $::env(VIV_SAVE)
+    variable g_project_save $::env(VIV_PROJECT)
 
     # Optional environment variables
     variable g_verilog_defs ""