fpga: tools: Fix VIVADO_PROJECT variable

Original-commit: 44e7651feee257319dff00577920fe5771473d62
2024-04-02 22:48:02 -05:00
parent 822d1bd26d
commit 1a4d0543f6
2 changed files with 2 additions and 2 deletions
@@ -26,7 +26,7 @@ namespace eval ::vivado_utils {
    variable g_output_dir   $::env(VIV_OUTPUT_DIR)
    variable g_source_files $::env(VIV_DESIGN_SRCS)
    variable g_vivado_mode  $::env(VIV_MODE)
-    variable g_project_save $::env(VIV_SAVE)
+    variable g_project_save $::env(VIV_PROJECT)

    # Optional environment variables
    variable g_verilog_defs ""