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fpga: tools: Fix VIVADO_PROJECT variable

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Original-commit: 44e7651feee257319dff00577920fe5771473d62
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Wade Fife committed 2024-04-02 22:48:02 -05:00
1 parent 822d1bd26d
commit 1a4d0543f6
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tools/scripts/viv_utils.tcl
+1 -1
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@@ -26,7 +26,7 @@ namespace eval ::vivado_utils {
variable g_output_dir $::env(VIV_OUTPUT_DIR)
variable g_source_files $::env(VIV_DESIGN_SRCS)
variable g_vivado_mode $::env(VIV_MODE)
variable g_project_save $::env(VIV_SAVE)
variable g_project_save $::env(VIV_PROJECT)
# Optional environment variables
variable g_verilog_defs ""