diff --git a/top/x400/doc/X4XX_FPGA_left.htm b/top/x400/doc/X4XX_FPGA_left.htm index 0a10171..d53fc9e 100644 --- a/top/x400/doc/X4XX_FPGA_left.htm +++ b/top/x400/doc/X4XX_FPGA_left.htm @@ -281,7 +281,8 @@

SPI_SLAVE_CONFIG

SPI_TRANSACTION_CONFIG

SPI_TRANSACTION_GO

-

SPI_STATUS

+

SPI_STATUS

+

CONTROLLER_INFO

diff --git a/top/x400/doc/X4XX_FPGA_right.htm b/top/x400/doc/X4XX_FPGA_right.htm index 0d8ec1c..ec5c993 100644 --- a/top/x400/doc/X4XX_FPGA_right.htm +++ b/top/x400/doc/X4XX_FPGA_right.htm @@ -3711,6 +3711,129 @@ Contains the status of the SPI engine. + + +

+ + +

Offset 0x001C: CONTROLLER_INFO Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + +
+ + + + +
RADIO_CTRLPORT_REGMAP|DIO_WINDOW
  0x00C000
+ +		 + + + + +
RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
  0x002000
+ +		 + + + + +
CONTROLLER_INFO
  offset=0x001C
+ +		 + + + + + +
+ + +Total Offset =
  0x00E01C + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_gpio_spi.v.

+ +
+ +
+ +Contains information pertaining this SPI controller block. + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..16 +

Reserved

+

+ +
15..8 +

Reserved

+

+ +
7..4 +

Reserved

+

+ +
3..0 +

SLAVE_COUNT

+

Indicates the number SPI slaves configurable by the controller.

+ +
+
@@ -24092,12 +24215,12 @@ FPGA version.
- 6 + 7 - 0x00000006 + 0x00000007 -

FPGA_CURRENT_VERSION_MINOR

+

FPGA_CURRENT_VERSION_MAJOR

@@ -24110,7 +24233,7 @@ FPGA version.
0x00000007 -

FPGA_CURRENT_VERSION_MAJOR

+

FPGA_CURRENT_VERSION_MINOR

@@ -24131,9 +24254,9 @@ FPGA version.
- 570565649 + 570622482 - 0x22022411 + 0x22030212

FPGA_VERSION_LAST_MODIFIED_TIME

diff --git a/top/x400/regmap/dig_ifc_regmap_utils.vh b/top/x400/regmap/dig_ifc_regmap_utils.vh index bca2c4d..21ce453 100644 --- a/top/x400/regmap/dig_ifc_regmap_utils.vh +++ b/top/x400/regmap/dig_ifc_regmap_utils.vh @@ -15,6 +15,7 @@ // SPI_TRANSACTION_CONFIG : 0x10 (x4xx_gpio_spi.v) // SPI_TRANSACTION_GO : 0x14 (x4xx_gpio_spi.v) // SPI_STATUS : 0x18 (x4xx_gpio_spi.v) + // CONTROLLER_INFO : 0x1C (x4xx_gpio_spi.v) //=============================================================================== // RegTypes @@ -82,6 +83,14 @@ localparam SPI_READY_MSB = 24; //SPI_STATUS:SPI_READY localparam SPI_READY = 24; //SPI_STATUS:SPI_READY + // CONTROLLER_INFO Register (from x4xx_gpio_spi.v) + localparam CONTROLLER_INFO = 'h1C; // Register Offset + localparam CONTROLLER_INFO_SIZE = 32; // register width in bits + localparam CONTROLLER_INFO_MASK = 32'hF; + localparam SLAVE_COUNT_SIZE = 4; //CONTROLLER_INFO:SLAVE_COUNT + localparam SLAVE_COUNT_MSB = 3; //CONTROLLER_INFO:SLAVE_COUNT + localparam SLAVE_COUNT = 0; //CONTROLLER_INFO:SLAVE_COUNT + // Return the offset of an element of register array SPI_SLAVE_CONFIG function integer SPI_SLAVE_CONFIG (input integer i); SPI_SLAVE_CONFIG = (i * 'h4) + 'h0; diff --git a/top/x400/regmap/versioning_regs_regmap_utils.vh b/top/x400/regmap/versioning_regs_regmap_utils.vh index 8928f06..84a5dd7 100644 --- a/top/x400/regmap/versioning_regs_regmap_utils.vh +++ b/top/x400/regmap/versioning_regs_regmap_utils.vh @@ -82,10 +82,10 @@ localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD - localparam FPGA_CURRENT_VERSION_MINOR = 'h6; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR + localparam FPGA_CURRENT_VERSION_MINOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22022411; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME + localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22030212; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME // Enumerated type RF_CORE_100M_VERSION localparam RF_CORE_100M_VERSION_SIZE = 7; diff --git a/top/x400/x4xx.v b/top/x400/x4xx.v index c16f551..07022a3 100644 --- a/top/x400/x4xx.v +++ b/top/x400/x4xx.v @@ -2284,12 +2284,12 @@ endmodule //
  • Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED // // -// +// // // // // -// +// // // // diff --git a/top/x400/x4xx_gpio_spi.v b/top/x400/x4xx_gpio_spi.v index a037ae1..314fda7 100644 --- a/top/x400/x4xx_gpio_spi.v +++ b/top/x400/x4xx_gpio_spi.v @@ -228,6 +228,10 @@ module x4xx_gpio_spi #( s_ctrlport_resp_data[SPI_RESPONSE_MSB:SPI_RESPONSE] <= readback[SPI_RESPONSE_MSB:SPI_RESPONSE]; end + BASE_ADDRESS + CONTROLLER_INFO: begin + s_ctrlport_resp_data[SLAVE_COUNT_MSB:SLAVE_COUNT] <= NUM_SLAVES; + end + // No register implementation for provided address default: begin // Acknowledge and provide error status if address is in range @@ -534,6 +538,14 @@ endmodule // Records the response of the last completed SPI transaction. // // +// +// +// Contains information pertaining this SPI controller block. +// +// +// Indicates the number SPI slaves configurable by the controller. +// +// // // //XmlParse xml_off