miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: tools: Add modelsim to make sim targets

Browse Source 
This adds a simulation make target that allows you to run ModelSim
natively rather than through Vivado.

Adds or modifies the following simulation make targets:
make vlint    - Brake up compilation to Verilog/SystemVerilog/VHDL
make modelsim - Depends on make vlint and invokes modelsim

Adds the following variables:
MODELSIM_ARGS - Added to invocation of ModelSim
SVLOG_ARGS    - Added to SystemVerilog invocation of vlog
VLOG_ARGS     - Added to Verilog invocation of vlog
VHDL_ARGS     - Added to VHDL invocation of vcom


Original-commit: b296b26053d4437b8ae97e3df415a3d041b7b51e
This commit is contained in:
Andrew Moch
2020-03-20 10:34:59 -05:00
committed by Wade Fife
parent 5367ec6006
commit 09751b661e
3 changed files with 124 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tools/scripts/viv_sim_project.tcl
+18 -14
View File
@@ -125,21 +125,25 @@ if [expr [string equal $simulator "Modelsim"] == 1] {
# Launch simulation
launch_simulation
# Synthesize requested modules
foreach synth_top "$::env(VIV_SYNTH_TOP)" {
set_property top $synth_top [current_fileset]
synth_design -mode out_of_context
# Perform a simple regex-based search for all clock signals and constrain
# them to 500 MHz for the timing report.
set clk_regexp "(?i)^(?!.*en.*).*(clk|clock).*"
foreach clk_inst [get_ports -regexp $clk_regexp] {
create_clock -name $clk_inst -period 2.0 [get_ports $clk_inst]
}
report_utilization -no_primitives -file ${working_dir}/${synth_top}_synth.rpt
report_timing_summary -setup -max_paths 3 -unique_pins -no_header -append -file ${working_dir}/${synth_top}_synth.rpt
write_checkpoint -force ${working_dir}/${synth_top}_synth.dcp
if { [info exists ::env(VIV_SYNTH_TOP)] } {
puts "BUILDER: Synthesizing"
# Synthesize requested modules
foreach synth_top "$::env(VIV_SYNTH_TOP)" {
set_property top $synth_top [current_fileset]
synth_design -mode out_of_context
# Perform a simple regex-based search for all clock signals and constrain
# them to 500 MHz for the timing report.
set clk_regexp "(?i)^(?!.*en.*).*(clk|clock).*"
foreach clk_inst [get_ports -regexp $clk_regexp] {
create_clock -name $clk_inst -period 2.0 [get_ports $clk_inst]
}
report_utilization -no_primitives -file ${working_dir}/${synth_top}_synth.rpt
report_timing_summary -setup -max_paths 3 -unique_pins -no_header -append -file ${working_dir}/${synth_top}_synth.rpt
write_checkpoint -force ${working_dir}/${synth_top}_synth.dcp
}
} else {
puts "BUILDER: Skipping resource report because VIV_SYNTH_TOP is not set"
}
# Close project
if [string equal $vivado_mode "batch"] {
puts "BUILDER: Closing project"