fpga: lib: Add ctrl_port_to_wb_i2c module
This module wraps i2c_master_top to provide a CtrlPort Interface. Original-commit: adceebe070d5b15be434aa07961958dafedf5095
This commit is contained in:
Ryan Marlow
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//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_to_i2c_tb
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//
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// Description:
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// testbench for ctrlport_to_i2c module. Tasks defined for ctrlport write and
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// read transactions as well as a task for waiting on the i2c transaction to
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// finish. Tests i2c write and reads.
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//
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`timescale 1ns / 1ps
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module ctrlport_to_i2c_tb();
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reg clk50;
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reg reset_clk50;
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reg s_ctrlport_req_wr;
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reg s_ctrlport_req_rd;
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reg [19:0] s_ctrlport_req_addr;
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reg [31:0] s_ctrlport_req_data;
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// Response
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wire s_ctrlport_resp_ack;
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wire [ 1:0] s_ctrlport_resp_status;
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wire [31:0] s_ctrlport_resp_data;
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wire i2c_scl_i, i2c_scl_o, i2c_sclen_o;
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wire i2c_sda_i, i2c_sda_o, i2c_sdaen_o;
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parameter SADR = 7'b010_0000;
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`include "../../../rfnoc/core/ctrlport.vh"
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`include "../../../wishbone/i2c_master.vh"
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task cp_write;
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input [19:0] a;
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input [31:0] d;
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begin
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s_ctrlport_req_addr = a;
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s_ctrlport_req_data = d;
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@(posedge clk50);
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s_ctrlport_req_wr = 1;
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@(posedge clk50);
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while(~s_ctrlport_resp_ack) @(posedge clk50);
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s_ctrlport_req_wr = 0;
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@(posedge clk50);
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end
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endtask
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task cp_read;
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input [19:0] a;
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input debug;
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begin
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s_ctrlport_req_addr = a;
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@(posedge clk50);
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s_ctrlport_req_rd = 1;
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@(posedge clk50);
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while(~s_ctrlport_resp_ack) @(posedge clk50);
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s_ctrlport_req_rd = 0;
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@(posedge clk50);
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if(debug) begin
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$display("status: read addr %h at %t value = %h", a, $time, s_ctrlport_resp_data);
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end
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end
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endtask
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task i2c_tip;
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begin
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$display("status: %t tip start", $time);
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cp_read('h0+WB_SR, 0);
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#1;
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while(s_ctrlport_resp_data[1])
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cp_read('h0+WB_SR, 0);
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$display("status: %t tip==0", $time);
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end
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endtask
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ctrlport_to_wb_i2c #( .BASE_ADDRESS(0)) ctrlport_to_wb_i2c_inst (
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.ctrlport_clk (clk50),
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.ctrlport_rst (reset_clk50),
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.s_ctrlport_req_wr (s_ctrlport_req_wr),
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.s_ctrlport_req_rd (s_ctrlport_req_rd),
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.s_ctrlport_req_addr (s_ctrlport_req_addr),
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.s_ctrlport_req_data (s_ctrlport_req_data),
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.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
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.s_ctrlport_resp_status (s_ctrlport_resp_status),
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.s_ctrlport_resp_data (s_ctrlport_resp_data),
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.scl_pad_i (i2c_scl_i),
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.scl_pad_o (i2c_scl_o),
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.scl_pad_en_o (i2c_sclen_o),
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.sda_pad_i (i2c_sda_i),
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.sda_pad_o (i2c_sda_o),
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.sda_pad_en_o (i2c_sdaen_o)
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);
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// hookup i2c slave model
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i2c_slave_model #(SADR) i2c_slave (
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.scl(i2c_scl_i),
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.sda(i2c_sda_i)
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);
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// create i2c lines
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delay m0_scl (i2c_sclen_o ? 1'bz : i2c_scl_o, i2c_scl_i),
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m0_sda (i2c_sdaen_o ? 1'bz : i2c_sda_o, i2c_sda_i);
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pullup p1(i2c_scl_i); // pullup scl line
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pullup p2(i2c_sda_i); // pullup sda line
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always #20 clk50 = ~clk50;
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initial begin
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clk50 = 0;
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reset_clk50 = 1;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 0;
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s_ctrlport_req_addr = 0;
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s_ctrlport_req_data = 0;
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repeat (5) @(posedge clk50);
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reset_clk50 = 0;
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repeat (5) @(posedge clk50);
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$display("status: %t done reset", $time);
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cp_write('h0+WB_PRER_LO, 'hF4); //F4
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cp_write('h0+WB_PRER_HI, 'h01); //1
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$display("status: %t set prescale to 500", $time);
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cp_read('h0+WB_PRER_LO, 1);
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cp_read('h0+WB_PRER_HI, 1);
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$display("status: %t enable core", $time);
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cp_write('h0+WB_CTR, 'h80);
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cp_write('h0+WB_TXR, {SADR,1'b0}); // present slave address, set write-bit
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cp_write('h0+WB_CR, CR_START_AND_WRITE); // set command (start, write)
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i2c_tip();
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cp_write('h0+WB_TXR, 'h01); // present slave address, set write-bit
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cp_write('h0+WB_CR, CR_WRITE); // set command (write)
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i2c_tip();
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// send memory contents
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cp_write('h0+WB_TXR, 8'ha5); // present data
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cp_write('h0+WB_CR, CR_WRITE); // set command (write)
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$display("status: %t write data a5", $time);
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i2c_tip();
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// send memory contents for next memory address (auto_inc)
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cp_write('h0+WB_TXR, 8'h5a); // present data
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cp_write('h0+WB_CR, CR_WRITE_AND_STOP); // set command (stop, write)
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$display("status: %t write next data 5a, generate 'stop'", $time);
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i2c_tip();
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// drive slave address
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cp_write('h0+WB_TXR, {SADR,1'b0} ); // present slave's address, set write-bit
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cp_write('h0+WB_CR, CR_START_AND_WRITE ); // set command (start, write)
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$display("status: %t generate 'repeated start', write cmd %0h (slave address+write)", $time, {SADR,1'b1} );
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i2c_tip();
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// send memory address
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cp_write('h0+WB_TXR, 8'h01); // present slave's memory address
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cp_write('h0+WB_CR, CR_WRITE); // set command (write)
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$display("status: %t write slave address 01", $time);
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i2c_tip();
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// drive slave address
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cp_write('h0+WB_TXR, {SADR,1'b1} ); // present slave's address, set read-bit
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cp_write('h0+WB_CR, CR_START_AND_WRITE ); // set command (start, write)
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$display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,1'b1} );
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i2c_tip();
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// read data from slave
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cp_write('h0+WB_CR, CR_READ_AND_ACK); // set command (read, ack_read)
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$display("status: %t read + ack", $time);
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i2c_tip();
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cp_read('h0+WB_RXR, 1);
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// read data from slave
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cp_write('h0+WB_CR, CR_READ_AND_ACK); // set command (read, ack_read)
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$display("status: %t read + ack", $time);
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i2c_tip();
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cp_read('h0+WB_RXR, 1);
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// read data from slave
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cp_write('h0+WB_CR, CR_READ_AND_ACK); // set command (read, ack_read)
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$display("status: %t read + ack", $time);
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i2c_tip();
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cp_read('h0+WB_RXR, 1);
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$display("status: %t simulation done", $time);
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$finish;
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end
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endmodule
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@@ -0,0 +1,358 @@
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant synthesizable I2C Slave model ////
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//// ////
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//// ////
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//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws ////
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//// John Sheahan (jrsheahan@optushome.com.au) ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001,2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: i2c_slave_model.v,v 1.7 2006-09-04 09:08:51 rherveille Exp $
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//
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// $Date: 2006-09-04 09:08:51 $
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// $Revision: 1.7 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2005/02/28 11:33:48 rherveille
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// Fixed Tsu:sta timing check.
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// Added Thd:sta timing check.
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//
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// Revision 1.5 2003/12/05 11:05:19 rherveille
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// Fixed slave address MSB='1' bug
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//
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// Revision 1.4 2003/09/11 08:25:37 rherveille
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// Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.
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//
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// Revision 1.3 2002/10/30 18:11:06 rherveille
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// Added timing tests to i2c_model.
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// Updated testbench.
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//
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// Revision 1.2 2002/03/17 10:26:38 rherveille
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// Fixed some race conditions in the i2c-slave model.
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// Added debug information.
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// Added headers.
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//
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`timescale 1ns / 10ps
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module i2c_slave_model (scl, sda);
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//
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// parameters
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//
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parameter I2C_ADR = 7'b001_0000;
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//
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// input && outpus
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//
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input scl;
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inout sda;
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//
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// Variable declaration
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//
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wire debug = 1'b1;
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reg [7:0] mem [7:0]; // initiate memory
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reg [7:0] mem_adr; // memory address
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reg [7:0] mem_do; // memory data output
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reg sta, d_sta;
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reg sto, d_sto;
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reg [7:0] sr; // 8bit shift register
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reg rw; // read/write direction
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wire my_adr; // my address called ??
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wire i2c_reset; // i2c-statemachine reset
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reg [2:0] bit_cnt; // 3bit downcounter
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wire acc_done; // 8bits transfered
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reg ld; // load downcounter
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reg sda_o; // sda-drive level
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wire sda_dly; // delayed version of sda
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// statemachine declaration
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parameter idle = 3'b000;
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parameter slave_ack = 3'b001;
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parameter get_mem_adr = 3'b010;
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parameter gma_ack = 3'b011;
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parameter data = 3'b100;
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parameter data_ack = 3'b101;
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reg [2:0] state; // synopsys enum_state
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//
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// module body
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//
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initial
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begin
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sda_o = 1'b1;
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state = idle;
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end
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// generate shift register
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always @(posedge scl)
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sr <= #1 {sr[6:0],sda};
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//detect my_address
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assign my_adr = (sr[7:1] == I2C_ADR);
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// FIXME: This should not be a generic assign, but rather
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// qualified on address transfer phase and probably reset by stop
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//generate bit-counter
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always @(posedge scl)
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if(ld)
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bit_cnt <= #1 3'b111;
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else
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bit_cnt <= #1 bit_cnt - 3'h1;
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//generate access done signal
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assign acc_done = !(|bit_cnt);
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// generate delayed version of sda
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// this model assumes a hold time for sda after the falling edge of scl.
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// According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
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// with regards to scl. If the data changes coincident with the clock, the
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// acknowledge is missed
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// Fix by Michael Sosnoski
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assign #1 sda_dly = sda;
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//detect start condition
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always @(negedge sda)
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if(scl)
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begin
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sta <= #1 1'b1;
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d_sta <= #1 1'b0;
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sto <= #1 1'b0;
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if(debug)
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$display("DEBUG i2c_slave; start condition detected at %t", $time);
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end
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else
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sta <= #1 1'b0;
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always @(posedge scl)
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d_sta <= #1 sta;
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// detect stop condition
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always @(posedge sda)
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if(scl)
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begin
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sta <= #1 1'b0;
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sto <= #1 1'b1;
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if(debug)
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$display("DEBUG i2c_slave; stop condition detected at %t", $time);
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end
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else
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sto <= #1 1'b0;
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//generate i2c_reset signal
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assign i2c_reset = sta || sto;
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// generate statemachine
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always @(negedge scl or posedge sto)
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if (sto || (sta && !d_sta) )
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begin
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state <= #1 idle; // reset statemachine
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sda_o <= #1 1'b1;
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ld <= #1 1'b1;
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end
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else
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begin
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// initial settings
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sda_o <= #1 1'b1;
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ld <= #1 1'b0;
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case(state) // synopsys full_case parallel_case
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idle: // idle state
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if (acc_done && my_adr)
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begin
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state <= #1 slave_ack;
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rw <= #1 sr[0];
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sda_o <= #1 1'b0; // generate i2c_ack
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#2;
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if(debug && rw)
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$display("DEBUG i2c_slave; command byte received (read) at %t", $time);
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if(debug && !rw)
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$display("DEBUG i2c_slave; command byte received (write) at %t", $time);
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if(rw)
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begin
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mem_do <= #1 mem[mem_adr];
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if(debug)
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begin
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#2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr);
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#2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]);
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end
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end
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end
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slave_ack:
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begin
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if(rw)
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begin
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state <= #1 data;
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sda_o <= #1 mem_do[7];
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end
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else
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state <= #1 get_mem_adr;
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ld <= #1 1'b1;
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end
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get_mem_adr: // wait for memory address
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if(acc_done)
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begin
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state <= #1 gma_ack;
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mem_adr <= #1 sr; // store memory address
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sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address
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if(debug)
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#1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o);
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end
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gma_ack:
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begin
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state <= #1 data;
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ld <= #1 1'b1;
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end
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data: // receive or drive data
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begin
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if(rw)
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sda_o <= #1 mem_do[7];
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if(acc_done)
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begin
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state <= #1 data_ack;
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mem_adr <= #2 mem_adr + 8'h1;
|
||||
sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read
|
||||
|
||||
if(rw)
|
||||
begin
|
||||
#3 mem_do <= mem[mem_adr];
|
||||
|
||||
if(debug)
|
||||
#5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr);
|
||||
end
|
||||
|
||||
if(!rw)
|
||||
begin
|
||||
mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory
|
||||
|
||||
if(debug)
|
||||
#2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
data_ack:
|
||||
begin
|
||||
ld <= #1 1'b1;
|
||||
|
||||
if(rw)
|
||||
if(sr[0]) // read operation && master send NACK
|
||||
begin
|
||||
state <= #1 idle;
|
||||
sda_o <= #1 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
state <= #1 data;
|
||||
sda_o <= #1 mem_do[7];
|
||||
end
|
||||
else
|
||||
begin
|
||||
state <= #1 data;
|
||||
sda_o <= #1 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
// read data from memory
|
||||
always @(posedge scl)
|
||||
if(!acc_done && rw)
|
||||
mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation
|
||||
|
||||
// generate tri-states
|
||||
assign sda = sda_o ? 1'bz : 1'b0;
|
||||
|
||||
|
||||
//
|
||||
// Timing checks
|
||||
//
|
||||
|
||||
wire tst_sto = sto;
|
||||
wire tst_sta = sta;
|
||||
|
||||
specify
|
||||
specparam normal_scl_low = 4700,
|
||||
normal_scl_high = 4000,
|
||||
normal_tsu_sta = 4700,
|
||||
normal_thd_sta = 4000,
|
||||
normal_tsu_sto = 4000,
|
||||
normal_tbuf = 4700,
|
||||
|
||||
fast_scl_low = 1300,
|
||||
fast_scl_high = 600,
|
||||
fast_tsu_sta = 1300,
|
||||
fast_thd_sta = 600,
|
||||
fast_tsu_sto = 600,
|
||||
fast_tbuf = 1300;
|
||||
|
||||
$width(negedge scl, normal_scl_low); // scl low time
|
||||
$width(posedge scl, normal_scl_high); // scl high time
|
||||
|
||||
$setup(posedge scl, negedge sda &&& scl, normal_tsu_sta); // setup start
|
||||
$setup(negedge sda &&& scl, negedge scl, normal_thd_sta); // hold start
|
||||
$setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // setup stop
|
||||
|
||||
$setup(posedge tst_sta, posedge tst_sto, normal_tbuf); // stop to start time
|
||||
endspecify
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -0,0 +1,464 @@
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// WISHBONE rev.B2 compliant I2C Master controller Testbench ////
|
||||
//// ////
|
||||
//// ////
|
||||
//// Author: Richard Herveille ////
|
||||
//// richard@asics.ws ////
|
||||
//// www.asics.ws ////
|
||||
//// ////
|
||||
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
|
||||
//// ////
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// Copyright (C) 2001 Richard Herveille ////
|
||||
//// richard@asics.ws ////
|
||||
//// ////
|
||||
//// This source file may be used and distributed without ////
|
||||
//// restriction provided that this copyright statement is not ////
|
||||
//// removed from the file and that any derivative work contains ////
|
||||
//// the original copyright notice and the associated disclaimer.////
|
||||
//// ////
|
||||
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
||||
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
||||
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
||||
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
||||
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
||||
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
||||
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
||||
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
||||
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
||||
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
||||
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
||||
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
||||
//// POSSIBILITY OF SUCH DAMAGE. ////
|
||||
//// ////
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
|
||||
// CVS Log
|
||||
//
|
||||
// $Id: tst_bench_top.v,v 1.8 2006-09-04 09:08:51 rherveille Exp $
|
||||
//
|
||||
// $Date: 2006-09-04 09:08:51 $
|
||||
// $Revision: 1.8 $
|
||||
// $Author: rherveille $
|
||||
// $Locker: $
|
||||
// $State: Exp $
|
||||
//
|
||||
// Change History:
|
||||
// $Log: not supported by cvs2svn $
|
||||
// Revision 1.7 2005/02/27 09:24:18 rherveille
|
||||
// Fixed scl, sda delay.
|
||||
//
|
||||
// Revision 1.6 2004/02/28 15:40:42 rherveille
|
||||
// *** empty log message ***
|
||||
//
|
||||
// Revision 1.4 2003/12/05 11:04:38 rherveille
|
||||
// Added slave address configurability
|
||||
//
|
||||
// Revision 1.3 2002/10/30 18:11:06 rherveille
|
||||
// Added timing tests to i2c_model.
|
||||
// Updated testbench.
|
||||
//
|
||||
// Revision 1.2 2002/03/17 10:26:38 rherveille
|
||||
// Fixed some race conditions in the i2c-slave model.
|
||||
// Added debug information.
|
||||
// Added headers.
|
||||
//
|
||||
|
||||
`timescale 1ns / 10ps
|
||||
|
||||
module tst_bench_top();
|
||||
|
||||
//
|
||||
// wires && regs
|
||||
//
|
||||
reg clk;
|
||||
reg rstn;
|
||||
|
||||
wire [31:0] adr;
|
||||
wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i;
|
||||
wire we;
|
||||
wire stb;
|
||||
wire cyc;
|
||||
wire ack;
|
||||
wire inta;
|
||||
|
||||
reg [7:0] q, qq;
|
||||
|
||||
wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
|
||||
wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen;
|
||||
|
||||
parameter PRER_LO = 3'b000;
|
||||
parameter PRER_HI = 3'b001;
|
||||
parameter CTR = 3'b010;
|
||||
parameter RXR = 3'b011;
|
||||
parameter TXR = 3'b011;
|
||||
parameter CR = 3'b100;
|
||||
parameter SR = 3'b100;
|
||||
|
||||
parameter TXR_R = 3'b101; // undocumented / reserved output
|
||||
parameter CR_R = 3'b110; // undocumented / reserved output
|
||||
|
||||
parameter RD = 1'b1;
|
||||
parameter WR = 1'b0;
|
||||
parameter SADR = 7'b0010_000;
|
||||
|
||||
//
|
||||
// Module body
|
||||
//
|
||||
|
||||
// generate clock
|
||||
always #5 clk = ~clk;
|
||||
|
||||
// hookup wishbone master model
|
||||
wb_master_model #(8, 32) u0 (
|
||||
.clk(clk),
|
||||
.rst(rstn),
|
||||
.adr(adr),
|
||||
.din(dat_i),
|
||||
.dout(dat_o),
|
||||
.cyc(cyc),
|
||||
.stb(stb),
|
||||
.we(we),
|
||||
.sel(),
|
||||
.ack(ack),
|
||||
.err(1'b0),
|
||||
.rty(1'b0)
|
||||
);
|
||||
|
||||
wire stb0 = stb & ~adr[3];
|
||||
wire stb1 = stb & adr[3];
|
||||
|
||||
assign dat_i = ({{8'd8}{stb0}} & dat0_i) | ({{8'd8}{stb1}} & dat1_i);
|
||||
|
||||
// hookup wishbone_i2c_master core
|
||||
i2c_master_top i2c_top (
|
||||
|
||||
// wishbone interface
|
||||
.wb_clk_i(clk),
|
||||
.wb_rst_i(1'b0),
|
||||
.arst_i(rstn),
|
||||
.wb_adr_i(adr[2:0]),
|
||||
.wb_dat_i(dat_o),
|
||||
.wb_dat_o(dat0_i),
|
||||
.wb_we_i(we),
|
||||
.wb_stb_i(stb0),
|
||||
.wb_cyc_i(cyc),
|
||||
.wb_ack_o(ack),
|
||||
.wb_inta_o(inta),
|
||||
|
||||
// i2c signals
|
||||
.scl_pad_i(scl),
|
||||
.scl_pad_o(scl0_o),
|
||||
.scl_padoen_o(scl0_oen),
|
||||
.sda_pad_i(sda),
|
||||
.sda_pad_o(sda0_o),
|
||||
.sda_padoen_o(sda0_oen)
|
||||
),
|
||||
i2c_top2 (
|
||||
|
||||
// wishbone interface
|
||||
.wb_clk_i(clk),
|
||||
.wb_rst_i(1'b0),
|
||||
.arst_i(rstn),
|
||||
.wb_adr_i(adr[2:0]),
|
||||
.wb_dat_i(dat_o),
|
||||
.wb_dat_o(dat1_i),
|
||||
.wb_we_i(we),
|
||||
.wb_stb_i(stb1),
|
||||
.wb_cyc_i(cyc),
|
||||
.wb_ack_o(ack),
|
||||
.wb_inta_o(inta),
|
||||
|
||||
// i2c signals
|
||||
.scl_pad_i(scl),
|
||||
.scl_pad_o(scl1_o),
|
||||
.scl_padoen_o(scl1_oen),
|
||||
.sda_pad_i(sda),
|
||||
.sda_pad_o(sda1_o),
|
||||
.sda_padoen_o(sda1_oen)
|
||||
);
|
||||
|
||||
|
||||
// hookup i2c slave model
|
||||
i2c_slave_model #(SADR) i2c_slave (
|
||||
.scl(scl),
|
||||
.sda(sda)
|
||||
);
|
||||
|
||||
// create i2c lines
|
||||
delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl),
|
||||
m1_scl (scl1_oen ? 1'bz : scl1_o, scl),
|
||||
m0_sda (sda0_oen ? 1'bz : sda0_o, sda),
|
||||
m1_sda (sda1_oen ? 1'bz : sda1_o, sda);
|
||||
|
||||
pullup p1(scl); // pullup scl line
|
||||
pullup p2(sda); // pullup sda line
|
||||
|
||||
initial
|
||||
begin
|
||||
`ifdef WAVES
|
||||
$shm_open("waves");
|
||||
$shm_probe("AS",tst_bench_top,"AS");
|
||||
$display("INFO: Signal dump enabled ...\n\n");
|
||||
`endif
|
||||
|
||||
force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
|
||||
// force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
|
||||
|
||||
$display("\nstatus: %t Testbench started\n\n", $time);
|
||||
|
||||
// $dumpfile("bench.vcd");
|
||||
// $dumpvars(1, tst_bench_top);
|
||||
// $dumpvars(1, tst_bench_top.i2c_slave);
|
||||
|
||||
// initially values
|
||||
clk = 0;
|
||||
|
||||
// reset system
|
||||
rstn = 1'b1; // negate reset
|
||||
#2;
|
||||
rstn = 1'b0; // assert reset
|
||||
repeat(1) @(posedge clk);
|
||||
rstn = 1'b1; // negate reset
|
||||
|
||||
$display("status: %t done reset", $time);
|
||||
|
||||
@(posedge clk);
|
||||
|
||||
//
|
||||
// program core
|
||||
//
|
||||
|
||||
// program internal registers
|
||||
u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
|
||||
u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
|
||||
u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
|
||||
$display("status: %t programmed registers", $time);
|
||||
|
||||
u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
|
||||
u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
|
||||
$display("status: %t verified registers", $time);
|
||||
|
||||
u0.wb_write(1, CTR, 8'h80); // enable core
|
||||
$display("status: %t core enabled", $time);
|
||||
|
||||
//
|
||||
// access slave (write)
|
||||
//
|
||||
|
||||
// drive slave address
|
||||
u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
|
||||
u0.wb_write(0, CR, 8'h90 ); // set command (start, write)
|
||||
$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(0, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
// send memory address
|
||||
u0.wb_write(1, TXR, 8'h01); // present slave's memory address
|
||||
u0.wb_write(0, CR, 8'h10); // set command (write)
|
||||
$display("status: %t write slave memory address 01", $time);
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(0, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
// send memory contents
|
||||
u0.wb_write(1, TXR, 8'ha5); // present data
|
||||
u0.wb_write(0, CR, 8'h10); // set command (write)
|
||||
$display("status: %t write data a5", $time);
|
||||
|
||||
while (scl) #1;
|
||||
force scl= 1'b0;
|
||||
#100000;
|
||||
release scl;
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(1, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
// send memory contents for next memory address (auto_inc)
|
||||
u0.wb_write(1, TXR, 8'h5a); // present data
|
||||
u0.wb_write(0, CR, 8'h50); // set command (stop, write)
|
||||
$display("status: %t write next data 5a, generate 'stop'", $time);
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(1, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
//
|
||||
// delay
|
||||
//
|
||||
// #100000; // wait for 100us.
|
||||
// $display("status: %t wait 100us", $time);
|
||||
|
||||
//
|
||||
// access slave (read)
|
||||
//
|
||||
|
||||
// drive slave address
|
||||
u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit
|
||||
u0.wb_write(0, CR, 8'h90 ); // set command (start, write)
|
||||
$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(1, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
// send memory address
|
||||
u0.wb_write(1, TXR, 8'h01); // present slave's memory address
|
||||
u0.wb_write(0, CR, 8'h10); // set command (write)
|
||||
$display("status: %t write slave address 01", $time);
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(1, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
// drive slave address
|
||||
u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit
|
||||
u0.wb_write(0, CR, 8'h90 ); // set command (start, write)
|
||||
$display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(1, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
// read data from slave
|
||||
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
|
||||
$display("status: %t read + ack", $time);
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(1, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
// check data just received
|
||||
u0.wb_read(1, RXR, qq);
|
||||
if(qq !== 8'ha5)
|
||||
$display("\nERROR: Expected a5, received %x at time %t", qq, $time);
|
||||
else
|
||||
$display("status: %t received %x", $time, qq);
|
||||
|
||||
// read data from slave
|
||||
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
|
||||
$display("status: %t read + ack", $time);
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(1, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
// check data just received
|
||||
u0.wb_read(1, RXR, qq);
|
||||
if(qq !== 8'h5a)
|
||||
$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
|
||||
else
|
||||
$display("status: %t received %x", $time, qq);
|
||||
|
||||
// read data from slave
|
||||
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
|
||||
$display("status: %t read + ack", $time);
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(1, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
// check data just received
|
||||
u0.wb_read(1, RXR, qq);
|
||||
$display("status: %t received %x from 3rd read address", $time, qq);
|
||||
|
||||
// read data from slave
|
||||
u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)
|
||||
$display("status: %t read + nack", $time);
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(1, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
// check data just received
|
||||
u0.wb_read(1, RXR, qq);
|
||||
$display("status: %t received %x from 4th read address", $time, qq);
|
||||
|
||||
//
|
||||
// check invalid slave memory address
|
||||
//
|
||||
|
||||
// drive slave address
|
||||
u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
|
||||
u0.wb_write(0, CR, 8'h90 ); // set command (start, write)
|
||||
$display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(1, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
// send memory address
|
||||
u0.wb_write(1, TXR, 8'h10); // present slave's memory address
|
||||
u0.wb_write(0, CR, 8'h10); // set command (write)
|
||||
$display("status: %t write slave memory address 10", $time);
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(1, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
// slave should have send NACK
|
||||
$display("status: %t Check for nack", $time);
|
||||
if(!q[7])
|
||||
$display("\nERROR: Expected NACK, received ACK\n");
|
||||
|
||||
// read data from slave
|
||||
u0.wb_write(1, CR, 8'h40); // set command (stop)
|
||||
$display("status: %t generate 'stop'", $time);
|
||||
|
||||
// check tip bit
|
||||
u0.wb_read(1, SR, q);
|
||||
while(q[1])
|
||||
u0.wb_read(1, SR, q); // poll it until it is zero
|
||||
$display("status: %t tip==0", $time);
|
||||
|
||||
#250000; // wait 250us
|
||||
$display("\n\nstatus: %t Testbench done", $time);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module delay (in, out);
|
||||
input in;
|
||||
output out;
|
||||
|
||||
assign out = in;
|
||||
|
||||
specify
|
||||
(in => out) = (600,600);
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -0,0 +1,206 @@
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// WISHBONE rev.B2 Wishbone Master model ////
|
||||
//// ////
|
||||
//// ////
|
||||
//// Author: Richard Herveille ////
|
||||
//// richard@asics.ws ////
|
||||
//// www.asics.ws ////
|
||||
//// ////
|
||||
//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////
|
||||
//// ////
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// Copyright (C) 2001 Richard Herveille ////
|
||||
//// richard@asics.ws ////
|
||||
//// ////
|
||||
//// This source file may be used and distributed without ////
|
||||
//// restriction provided that this copyright statement is not ////
|
||||
//// removed from the file and that any derivative work contains ////
|
||||
//// the original copyright notice and the associated disclaimer. ////
|
||||
//// ////
|
||||
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
||||
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
||||
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
||||
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
||||
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
||||
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
||||
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
||||
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
||||
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
||||
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
||||
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
||||
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
||||
//// POSSIBILITY OF SUCH DAMAGE. ////
|
||||
//// ////
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
// CVS Log
|
||||
//
|
||||
// $Id: wb_master_model.v,v 1.4 2004-02-28 15:40:42 rherveille Exp $
|
||||
//
|
||||
// $Date: 2004-02-28 15:40:42 $
|
||||
// $Revision: 1.4 $
|
||||
// $Author: rherveille $
|
||||
// $Locker: $
|
||||
// $State: Exp $
|
||||
//
|
||||
// Change History:
|
||||
//
|
||||
`timescale 1ns / 10ps
|
||||
|
||||
|
||||
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
|
||||
|
||||
parameter dwidth = 32;
|
||||
parameter awidth = 32;
|
||||
|
||||
input clk, rst;
|
||||
output [awidth -1:0] adr;
|
||||
input [dwidth -1:0] din;
|
||||
output [dwidth -1:0] dout;
|
||||
output cyc, stb;
|
||||
output we;
|
||||
output [dwidth/8 -1:0] sel;
|
||||
input ack, err, rty;
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Local Wires
|
||||
//
|
||||
|
||||
reg [awidth -1:0] adr;
|
||||
reg [dwidth -1:0] dout;
|
||||
reg cyc, stb;
|
||||
reg we;
|
||||
reg [dwidth/8 -1:0] sel;
|
||||
|
||||
reg [dwidth -1:0] q;
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Memory Logic
|
||||
//
|
||||
|
||||
initial
|
||||
begin
|
||||
//adr = 32'hxxxx_xxxx;
|
||||
//adr = 0;
|
||||
adr = {awidth{1'bx}};
|
||||
dout = {dwidth{1'bx}};
|
||||
cyc = 1'b0;
|
||||
stb = 1'bx;
|
||||
we = 1'hx;
|
||||
sel = {dwidth/8{1'bx}};
|
||||
#1;
|
||||
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Wishbone write cycle
|
||||
//
|
||||
|
||||
task wb_write;
|
||||
input delay;
|
||||
integer delay;
|
||||
|
||||
input [awidth -1:0] a;
|
||||
input [dwidth -1:0] d;
|
||||
|
||||
begin
|
||||
|
||||
// wait initial delay
|
||||
repeat(delay) @(posedge clk);
|
||||
|
||||
// assert wishbone signal
|
||||
#1;
|
||||
adr = a;
|
||||
dout = d;
|
||||
cyc = 1'b1;
|
||||
stb = 1'b1;
|
||||
we = 1'b1;
|
||||
sel = {dwidth/8{1'b1}};
|
||||
@(posedge clk);
|
||||
|
||||
// wait for acknowledge from slave
|
||||
while(~ack) @(posedge clk);
|
||||
|
||||
// negate wishbone signals
|
||||
#1;
|
||||
cyc = 1'b0;
|
||||
stb = 1'bx;
|
||||
adr = {awidth{1'bx}};
|
||||
dout = {dwidth{1'bx}};
|
||||
we = 1'hx;
|
||||
sel = {dwidth/8{1'bx}};
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Wishbone read cycle
|
||||
//
|
||||
|
||||
task wb_read;
|
||||
input delay;
|
||||
integer delay;
|
||||
|
||||
input [awidth -1:0] a;
|
||||
output [dwidth -1:0] d;
|
||||
|
||||
begin
|
||||
|
||||
// wait initial delay
|
||||
repeat(delay) @(posedge clk);
|
||||
|
||||
// assert wishbone signals
|
||||
#1;
|
||||
adr = a;
|
||||
dout = {dwidth{1'bx}};
|
||||
cyc = 1'b1;
|
||||
stb = 1'b1;
|
||||
we = 1'b0;
|
||||
sel = {dwidth/8{1'b1}};
|
||||
@(posedge clk);
|
||||
|
||||
// wait for acknowledge from slave
|
||||
while(~ack) @(posedge clk);
|
||||
|
||||
// negate wishbone signals
|
||||
#1;
|
||||
cyc = 1'b0;
|
||||
stb = 1'bx;
|
||||
adr = {awidth{1'bx}};
|
||||
dout = {dwidth{1'bx}};
|
||||
we = 1'hx;
|
||||
sel = {dwidth/8{1'bx}};
|
||||
d = din;
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Wishbone compare cycle (read data from location and compare with expected data)
|
||||
//
|
||||
|
||||
task wb_cmp;
|
||||
input delay;
|
||||
integer delay;
|
||||
|
||||
input [awidth -1:0] a;
|
||||
input [dwidth -1:0] d_exp;
|
||||
|
||||
begin
|
||||
wb_read (delay, a, q);
|
||||
|
||||
if (d_exp !== q)
|
||||
$display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
|
||||
end
|
||||
endtask
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
Reference in New Issue
Block a user